myfx2.v

usb cy7c68013开发板中CPLD的源代码

module MYFX2 (
               BKPT,nRESET,nPSEN,CLKOUT,nRD,nWR,IFCLK,	// Inputs from FX2
               PB,FXA,PA,PE,                //Inputs from FX2
		           RDY,CTL,                     //Inputs from FX2
		           MM1,MM0,	                // mem select jumpers
		           S1,S2,S3,MCLK,               //function select jumpers
		           
 			EA,	USBCLK,		// Output to FX2		  
		  
		  SIO,			// IO for client		
		  LED,		    // LED indicator
		  nRAMCE,nRAMOE,nRAMWR,RAMA16,	// outputs to  program RAM
		  nRWE,nROE,nRCS,                // outputs to test RAM
		  BKMONLED);		// Breakpoint/Monitor LED (green)
		  				
input   [7:0]PB;
input	[15:8]FXA;
//input   [7:0]PA;
input   [7:0]PE;
input  [2:0]RDY;
input  [5:0]CTL;

input   BKPT,nRESET,nPSEN,CLKOUT,nRD,nWR,MM1,MM0,IFCLK;
input    S1,S2,S3,MCLK;

output   [7:0]PA;
output	EA,nRWE,nROE,nRCS;
output  [7:0]LED;
output	nRAMCE,nRAMOE,nRAMWR,RAMA16,BKMONLED;
output  [18:1]SIO;
output  USBCLK;

assign BKMONLED = !BKPT;
assign USBCLK = MCLK;

assign PA[2] = 0;
assign PA[6] = 1;





assign SIO[1] = FXA[8];
assign SIO[2] = FXA[9];
assign SIO[3] = FXA[10];
assign SIO[4] = FXA[11];
assign SIO[5] = FXA[12];
assign SIO[6] = FXA[13];
assign SIO[7] = FXA[14];
assign SIO[8] = FXA[15];

assign SIO[9] = PE[0];
assign SIO[10] = PE[1];
assign SIO[11] = PE[2];
assign SIO[12] = PE[3];
assign SIO[13] = PE[4];
assign SIO[14] = PE[5];
assign SIO[15] = PE[6];
assign SIO[16] = PE[7];

assign SIO[17] = CLKOUT;
assign SIO[18] = IFCLK;


assign  nRCS = CTL[3];
assign  nROE = CTL[4];
assign  nRWE = CTL[5];


				

// Define 4 external memory maps based on two jumpers MM1-MM0
// 00: Internal code/data mem at 0000-1FFF
//	  No external memory (FX2 single chip operation)
// 01: Internal code/data mem at 0000-1FFF
//	  External code/data mem at 8000-FFFF
// 10: Internal data mem at 0000-1FFF
//	  External code mem at 0000-FFFF, data mem at 2000-FFFF
// 11: Internal code/data mem at 0000-1FFF, (DEFAULT)
//	  External code/data mem at 2000-FFFF

assign RAMA16 = 0;				// no bank switching
wire a15 = FXA[15];			// for Warp
reg nRAMCE,nRAMOE,nRAMWR,EA;


//assign LED[0] = PB[0];	
//assign LED[1] = PB[1];	
//assign LED[2] = PB[2];	
//assign LED[3] = PB[3];	
//assign LED[4] = PB[4];	
//assign LED[5] = PB[5];	
//assign LED[6] = PB[6];	
//assign LED[7] = PB[7];	



always @ (MM1 or MM0 or nRD or nPSEN or nWR or a15)
	case ({MM1,MM0})
		2'b00	:			// no external memory	
			begin	
			nRAMCE = 1;
			nRAMOE = 1;
			nRAMWR = 1;	
			EA  = 0;	// Use internal prog mem at 0000-1FFF
			end
		2'b01:				// 32KB pgm/data memory at 8000-FFFF
			begin
			nRAMCE = !a15;		// Top 32K only enabled
			nRAMOE = !(!nRD | !nPSEN);  // combined pgm & data memory
			nRAMWR = nWR;	// FX2 gates nRD,nWR,nPSEN for outside access
			EA = 0;	   // Use internal prog mem at 0000-1FFF
			end
		2'b10:				// 64K pgm, 56K data
			begin
			nRAMCE = 0;		// entire RAM enabled
			nRAMOE = !(!nRD | !nPSEN);// combined pgm & data memory
			nRAMWR = nWR;	// FX2 gates nRD,nWR,nPSEN for outside access
			EA  =	1;   // Use EXTERNAL prog mem at 0000-1FFF
			end
		2'b11	:		// 56K pgm, 56K data
			begin				
			nRAMCE = 0;	// entire RAM enabled
			nRAMOE = !(!nRD | !nPSEN);  // combined pgm & data memory
			nRAMWR = nWR;	// FX2 gates nRD,nWR,nPSEN for outside access
			EA = 0;	// Use internal mem at 0000-1FFF
			end
	endcase	
	
	
	
reg L0,L1,L2,L3,L4,L5,L6,L7;
always @ (S1 or S2 or S3 or  nRD or  nRESET or a15 or nWR)
if (!nRESET)
	begin	L0=1; L1=1;L2=1; L3=1; L4=1; L5=1;L6=1; L7=1; end
else
case ({S1,S2,S3})
   2'b000:
    begin
   		case (FXA[15:8])
		8'h80:	L0=0;					// LED2 on
		8'h81:	L0=1;					// off
		8'h90:	L1=0;					// LED3 on
		8'h91:	L1=1;					// off
		8'hA0:	L2=0;					// LED4 on
		8'hA1:	L2=1;					// off
		8'hB0:	L3=0;					// LED5 on
		8'hB1:	L3=1;					// off
	    endcase
	end
	2'b001:
    begin
   		L0=PB[0];					// LED2 on
		L1=PB[1];					// off
		L2=PB[2];					// LED3 on
		L3=PB[3];					// off
		L4=PB[4];					// LED4 on
		L5=PB[5];					// off
		L6=PB[6];					// LED5 on
		L7=PB[7];					// off
	end
	2'b010:
    begin
   		//L5=CTL[1];					// LED2 on
		L6=CTL[1];					// off
		L7=CTL[2];
	  //case (FXA[15:8])
		//8'h80:	L0=0;					// LED2 on
		//8'h81:	L0=1;					// off
		//8'h90:	L1=0;					// LED3 on
		//8'h91:	L1=1;					// off
		//8'hA0:	L2=0;					// LED4 on
		//8'hA1:	L2=1;					// off
		//8'hB0:	L3=0;					// LED5 on
		//8'hB1:	L3=1;					// off
	    //endcase	
	end
endcase

//assign LED2	= L2;
//assign LED3	= L3;	
//assign LED4	= L4;	
//assign LED5	= L5


assign LED[0] = L0;	
assign LED[1] = L1;	
assign LED[2] = L2;	
assign LED[3] = L3;	
assign LED[4] = L4;	
assign LED[5] = L5;	
assign LED[6] = L6;	
assign LED[7] = L7;
												
endmodule