sysctrl.c.bak

2812 开发库

#include "DSP281x_Device.h"
#include "IO_DEFINE.h"



/**********************************************************************
* Function: InitSysCtrl()
*
* Description: Initializes the F281x CPU.
**********************************************************************/
void InitSysCtrl(void)
{
volatile int16 dummy;					// General purpose volatile int

	asm(" EALLOW");						// Enable EALLOW protected register access

/*** Memory Protection Configuration ***/
	DevEmuRegs.PROTSTART = 0x0100;		// Write default value to protection start register
	DevEmuRegs.PROTRANGE = 0x00FF;		// Write default value to protection range register

/*** Unlock the Code Security Module if CSM not in use ***/
/* Unlocking the CSM will allow code running from non-secure memory
   to access code and data in secure memory.  One would only want to
   unsecure the CSM if code security were not desired, and therefore
   the CSM is not in use (otherwise, unlocking the CSM will compromise
   the security of user code).  If the CSM is not in use, the best
   thing to do is leave the password locations programmed to 0xFFFF,
   which is the flash ERASED state.  When all passwords are 0xFFFF,
   all that is required to unlock the CSM are dummy reads of the
   PWL locations.*/
	dummy = CsmPwl.PSWD0;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD1;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD2;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD3;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD4;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD5;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD6;				// Dummy read of PWL locations
	dummy = CsmPwl.PSWD7;				// Dummy read of PWL locations

/*** Disable the Watchdog Timer ***/
	SysCtrlRegs.WDCR = 0x00E8;
/*
 bit 15-8      0's:    reserved
 bit 7         1:      WDFLAG, write 1 to clear
 bit 6         1:      WDDIS, 1=disable WD
 bit 5-3       101:    WDCHK, WD check bits, always write as 101b
 bit 2-0       000:    WDPS, WD prescale bits, 000: WDCLK=OSCCLK/512/1
*/

/* System and Control Register */
	SysCtrlRegs.SCSR = 0x0002;
/*
 bit 15-3      0's:    reserved
 bit 2         0:      WDINTS, WD interrupt status bit (read-only)
 bit 1         1:      WDENINT, 0=WD causes reset, 1=WD causes WDINT
 bit 0         0:      WDOVERRIDE, write 1 to disable disabling of the WD (clear-only)
*/

/*** Configure the PLL and clocks ***/
/* DSP/BIOS configures the PLL after main() is run to the value specified in the DSP/BIOS
   configuration tool.  You can configure the PLL below instead if you want the PLL running
   earlier in the initialization process.
*/
	SysCtrlRegs.PLLCR.all = 0x000A;			// PLLx5

	SysCtrlRegs.HISPCP.all = 0x0000;		// Hi-speed periph clock prescaler, HSPCLK=SYSCLKOUT/1
	SysCtrlRegs.LOSPCP.all = 0x0002;		// Lo-speed periph clock prescaler, LOSPCLK=SYSCLKOUT/4

	SysCtrlRegs.PCLKCR.bit.ECANENCLK = 1;	// SYSCLK to CAN enabled
	SysCtrlRegs.PCLKCR.bit.SCIBENCLK = 1;	// LSPCLK to SCIB enabled
	SysCtrlRegs.PCLKCR.bit.SCIAENCLK = 1;	// LSPCLK to SCIA enabled
	SysCtrlRegs.PCLKCR.bit.SPIENCLK = 1;	// LSPCLK to SPI enabled
	SysCtrlRegs.PCLKCR.bit.ADCENCLK = 1;	// HSPCLK to ADC enabled
	SysCtrlRegs.PCLKCR.bit.EVAENCLK = 1;	// HSPCLK to EVA enabled

/*** Configure the low-power modes ***/
	SysCtrlRegs.LPMCR0.all = 0x00FC;		// LPMCR0 set to default value
	SysCtrlRegs.LPMCR1.all = 0x0000;		// LPMCR1 set to default value

/*** Finish up ***/
	asm(" EDIS");						// Disable EALLOW protected register access

} //end InitSysCtrl()


/**********************************************************************
* Function: InitFlash()
* Description: Initializes the F281x flash timing registers.
* Notes:
*  1) This function MUST be executed out of RAM.  Executing it out of
*     OTP/FLASH will produce unpredictable results.
*  2) The flash registers are code security module protected.  Therefore,
*     you must either run this function from L0/L1 RAM, or you must
*     first unlock the CSM.  Note that unlocking the CSM as part of
*     the program flow can compromise the code security.
*  3) Final flash characterization needs to be performed by TI.  The
*     below settings may not meet final specifications, and are for
*     example purposes only.  Check the latest device datasheet for 
*     TMS qualified specifications.
**********************************************************************/
#pragma CODE_SECTION(InitFlash, "secureRamFuncs")
void InitFlash(void)
{
	asm(" EALLOW");									// Enable EALLOW protected register access
	FlashRegs.FPWR.bit.PWR = 3;						// Pump and bank set to active mode
	FlashRegs.FSTATUS.bit.V3STAT = 1;				// Clear the 3VSTAT bit
	FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;	// Sleep to standby transition cycles
	FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;	// Standby to active transition cycles
	FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;			// Random access waitstates
	FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;			// Paged access waitstates
	FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;				// Random access waitstates
	FlashRegs.FOPT.bit.ENPIPE = 1;					// Enable the flash pipeline
	asm(" EDIS");									// Disable EALLOW protected register access

/*** Force a complete pipeline flush to ensure that the write to the last register
     configured occurs before returning.  Safest thing is to wait 8 full cycles. ***/

    asm(" RPT #8 || NOP");

} //end of InitFlash()


/**********************************************************************
* Function: InitXintf()
*
* Description: Initializes the external memory interface on the F2812.
**********************************************************************/
void InitXintf(void)
{

/*** XINTCNF2 Register ***/
	XintfRegs.XINTCNF2.bit.XTIMCLK = 0;			// XTIMCLK=SYSCLKOUT/1
	XintfRegs.XINTCNF2.bit.CLKOFF = 0;			// XCLKOUT is enabled
	XintfRegs.XINTCNF2.bit.CLKMODE = 0;			// XCLKOUT = XTIMCLK

// Make sure write buffer is empty before configuring buffering depth
	while(XintfRegs.XINTCNF2.bit.WLEVEL != 0);	// poll the WLEVEL bit
	XintfRegs.XINTCNF2.bit.WRBUFF = 0;			// No write buffering

/*** XBANK Register ***/
// Example: Assume Zone 2 is slow, so add additional BCYC cycles whenever
// switching from Zone 2 to another Zone.  This will help avoid bus contention.
	XintfRegs.XBANK.bit.BCYC = 7;				// Add 7 cycles
	XintfRegs.XBANK.bit.BANK = 2;				// select zone 2
    
/*** Zone 0 Configuration ***/

/*** Zone 1 Configuration ***/

/*** Zone 2 Configuration ***/
	XintfRegs.XTIMING2.bit.X2TIMING = 1;	// Timing scale factor = 2
	XintfRegs.XTIMING2.bit.XSIZE = 3;		// Always write as 11b
	XintfRegs.XTIMING2.bit.READYMODE = 1; 	// XREADY is asynchronous
    XintfRegs.XTIMING2.bit.USEREADY = 0;	// Disable XREADY
	XintfRegs.XTIMING2.bit.XRDLEAD = 1;		// Read lead time
	XintfRegs.XTIMING2.bit.XRDACTIVE = 7;	// Read active time
	XintfRegs.XTIMING2.bit.XRDTRAIL = 1;	// Read trail time
	XintfRegs.XTIMING2.bit.XWRLEAD = 1;		// Write lead time
	XintfRegs.XTIMING2.bit.XWRACTIVE = 7;	// Write active time
	XintfRegs.XTIMING2.bit.XWRTRAIL = 1;	// Write trail time

/*** Zone 6 Configuration ***/
	XintfRegs.XTIMING6.bit.X2TIMING = 0;	// Timing scale factor = 1
	XintfRegs.XTIMING6.bit.XSIZE = 3;		// Always write as 11b
	XintfRegs.XTIMING6.bit.READYMODE = 1; 	// XREADY is asynchronous
	XintfRegs.XTIMING6.bit.USEREADY = 0;	// Disable XREADY
	XintfRegs.XTIMING6.bit.XRDLEAD = 1;		// Read lead time
	XintfRegs.XTIMING6.bit.XRDACTIVE = 2;	// Read active time
	XintfRegs.XTIMING6.bit.XRDTRAIL = 0;	// Read trail time
	XintfRegs.XTIMING6.bit.XWRLEAD = 1;		// Write lead time
	XintfRegs.XTIMING6.bit.XWRACTIVE = 2;	// Write active time
	XintfRegs.XTIMING6.bit.XWRTRAIL = 0;	// Write trail time

/*** Zone 7 Configuration ***/
	XintfRegs.XTIMING7.bit.X2TIMING = 0;	// Timing scale factor = 1
	XintfRegs.XTIMING7.bit.XSIZE = 3;		// Always write as 11b
	XintfRegs.XTIMING7.bit.READYMODE = 1; 	// XREADY is asynchronous
	XintfRegs.XTIMING7.bit.USEREADY = 0;	// Disable XREADY
	XintfRegs.XTIMING7.bit.XRDLEAD = 1;		// Read lead time
	XintfRegs.XTIMING7.bit.XRDACTIVE = 2;	// Read active time
	XintfRegs.XTIMING7.bit.XRDTRAIL = 0;	// Read trail time
	XintfRegs.XTIMING7.bit.XWRLEAD = 1;		// Write lead time
	XintfRegs.XTIMING7.bit.XWRACTIVE = 2;	// Write active time
	XintfRegs.XTIMING7.bit.XWRTRAIL = 0;	// Write trail time

/*** Force a complete pipeline flush to ensure that the write to the last register
     configured occurs before returning.  Safest thing to do is wait 8 full cycles.
***/
	asm(" RPT #6 || NOP");


} //end of InitXintf()

/**********************************************************************
* Function: InitGpio()
*
* Description: Initializes the shared GPIO pins on the F281x.
**********************************************************************/
void InitGpio(void)
{
	asm(" EALLOW");						// Enable EALLOW protected register access

/*** Group A pins ***/
	GpioMuxRegs.GPAQUAL.all=0x0020;					// Input qualifier 64X
	GpioMuxRegs.GPADIR.all = 0x00FF;				// BITS 0-7 are outputs

	GpioMuxRegs.GPAMUX.bit.CAP1Q1_GPIOA8   = 1;		// 1: CAP1--/50HZ

/*** Group B pins ***/
	GpioMuxRegs.GPBQUAL.all = 0x0020;		// Input qualifier 64X
	GpioMuxRegs.GPBDIR.all = 0x3FFF;		// BITS 14,15 are inputs
	GpioMuxRegs.GPBMUX.all  = 0x0000;		// 0: select GPIO function

/*** Group D pins ***/
	GpioMuxRegs.GPDQUAL.all=0x0020;					// Input qualifier 64X
	GpioMuxRegs.GPDDIR.all = 0x0060;				// BIT 5,6 is output
	GpioMuxRegs.GPDMUX.all = 0x0000;	            // 0: select GPIO function

/*** Group E pins ***/
	GpioMuxRegs.GPEQUAL.all=0x0001;					// Input qualifier 2X
	GpioMuxRegs.GPEDIR.all = 0x0000;				//intput

	GpioMuxRegs.GPEMUX.bit.XNMI_XINT13_GPIOE2  = 0;	// GPIO
	GpioMuxRegs.GPEMUX.bit.XINT2_ADCSOC_GPIOE1 = 0;	// GPIO
	GpioMuxRegs.GPEMUX.bit.XINT1_XBIO_GPIOE0   = 1;	// function INT

/*** Group F pins ***/
	GpioMuxRegs.GPFDIR.all = 0x7F04;				// 

	GpioMuxRegs.GPFMUX.bit.XF_GPIOF14      = 0;		// 0: select GPIO function
	GpioMuxRegs.GPFMUX.bit.MDRA_GPIOF13    = 0;		// 0: select GPIO function
	GpioMuxRegs.GPFMUX.bit.MDXA_GPIOF12    = 0;		// 0: select GPIO function
	GpioMuxRegs.GPFMUX.bit.MFSRA_GPIOF11   = 0;		// 0: select GPIO function
	GpioMuxRegs.GPFMUX.bit.MFSXA_GPIOF10   = 0;		// 0: select GPIO function
	GpioMuxRegs.GPFMUX.bit.MCLKRA_GPIOF9   = 0;		// 0: select GPIO function
	GpioMuxRegs.GPFMUX.bit.MCLKXA_GPIOF8   = 0;		// 0: select GPIO function
	GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7   = 1;		// CANRX
	GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6   = 1;		// CANTX
	GpioMuxRegs.GPFMUX.bit.SCIRXDA_GPIOF5  = 1;		// SCIRXDA
	GpioMuxRegs.GPFMUX.bit.SCITXDA_GPIOF4  = 1;		// SCITXDA
	GpioMuxRegs.GPFMUX.bit.SPISTEA_GPIOF3  = 0;		// 0: select GPIO function
	GpioMuxRegs.GPFMUX.bit.SPICLKA_GPIOF2  = 1;		// SPICLK
	GpioMuxRegs.GPFMUX.bit.SPISOMIA_GPIOF1 = 1;		// SPISOMI
	GpioMuxRegs.GPFMUX.bit.SPISIMOA_GPIOF0 = 1;		// SPISIMO

/*** Group G pins ***/
	GpioMuxRegs.GPGDIR.all = 0x0000;				// All group G GPIO are inputs

	GpioMuxRegs.GPGMUX.bit.SCIRXDB_GPIOG5  = 1;		// SCIRXDB
	GpioMuxRegs.GPGMUX.bit.SCITXDB_GPIOG4  = 1;		// SCITXDB

/*** Finish up ***/
	asm(" EDIS");						// Disable EALLOW protected register access

} //end InitGpio()


/**********************************************************************
* Function: InitEv()
*
* Description: Initializes the Event Managers on the F281x.
**********************************************************************/
void InitEv(void)
{

/**************************************/
/*** Configure the EXTCON registers ***/
/**************************************/
	EvaRegs.EXTCONA.all = 0x0001;
/*
 bit 15-4      0's:    reserved
 bit 3         0:      EVSOCE, 0 = disable EV start of ADC conversion output
 bit 2         0:      QEPIE, 0 = disable CAP3_QEPI as index input
 bit 1         0:      QEPIQUAL, 0 = CAP3_QEPI qual disabled
 bit 0         1:      INDCOE, 1 = independent compare enable
*/

/******************************************************/
/*** Disable and clear all event manager interrupts ***/
/******************************************************/
	EvaRegs.EVAIMRA.all = 0x0000;		// Disable all EVA group A interrupts
	EvaRegs.EVAIMRB.all = 0x0000;		// Disable all EVA group B interrupts
    EvaRegs.EVAIMRC.all = 0x0000;		// Disable all EVA group C interrupts
    EvaRegs.EVAIFRA.all = 0xFFFF;       // Clear all EVA group A interrupts
    EvaRegs.EVAIFRB.all = 0xFFFF;		// Clear all EVA group B interrupts
    EvaRegs.EVAIFRC.all = 0xFFFF;		// Clear all EVA group C interrupts

/**************************************/
/*** Configure the GPTCONA register ***/
/**************************************/
	EvaRegs.GPTCONA.all = 0x0400;
/*
 bit 15        0:      reserved
 bit 14        0:      T2STAT, read-only
 bit 13        0:      T1STAT, read-only
 bit 12        0:      T2CTRIPE, 0=disable timer2 compare trip
 bit 11        0:      T1CTRIPE, 0=disable timer1 compare trip
 bit 10-9      10:     T2TOADC, 10 = timer2 period flag starts ADC
 bit 8-7       00:     T1TOADC, 00 = timer1 does not start ADC
 bit 6         0:      TCOMPOE, 0 = Hi-z all timer compare outputs
 bit 5         0:      T2COMPOE, 0 = timer2 compare HI-z'd
 bit 4         0:      T1COMPOE, 0 = timer1 compare HI-z'd
 bit 3-2       00:     T2PIN, 00 = forced low
 bit 1-0       00:     T1PIN, 00 = forced low
*/


/************************************************************/
/*** Configure Timer 2 to trigger the ADC at a 50KHz rate ***/
/************************************************************/
	EvaRegs.T2CON.all = 0x0000;			// Disable timer
	EvaRegs.T2CNT = 0x0000;				// Clear timer counter
    EvaRegs.T2PR = 46874;           	// Set timer period 20ms/64

	EvaRegs.T2CON.all = 0xD040;			//enable timer
/*
 bit 15-14     11:     FREE/SOFT, 11 = ignor emulation suspend
 bit 13        0:      reserved
 bit 12-11     10:     TMODEx, 10 = continuous-up count mode
 bit 10-8      000:    TPSx, 000 = x/1 prescaler
 bit 7         0:      T2SWT1, 0 = use own TENABLE bit
 bit 6         1:      TENABLE, 1 = enable timer
 bit 5-4       00:     TCLKS, 00 = HSPCLK is clock source
 bit 3-2       00:     TCLD, 00 = reload compare reg on underflow
 bit 1         0:      TECMPR, 0 = enable timer compare
 bit 0         0:      SELT1PR, 0 = use own period register
*/

/************************************************************/
/*** Configure Timer 1 for cap1 ***/
/************************************************************/
	EvaRegs.T1CON.all = 0x0000;			// Disable timer
	EvaRegs.T1CNT = 0x0000;				// Clear timer counter
    EvaRegs.T1PR = 0xFFFF;		// Set timer period

	EvaRegs.T1CON.all = 0xD640;			// Init T1CON, enable timer
/*
 bit 15-14     11:     FREE/SOFT, 11 = ignor emulation suspend
 bit 13        0:      reserved
 bit 12-11     10:     TMODEx, 10 = continous-up count mode
 bit 10-8      110:    TPSx, 110 = x/64 prescaler
 bit 7         0:      T2SWT1, 0 = use own TENABLE bit
 bit 6         1:      TENABLE, 1 = enable timer
 bit 5-4       00:     TCLKS, 00 = CPUCLK is clock source
 bit 3-2       00:     TCLD, 00 = reload compare reg on underflow
 bit 1         0:      TECMPR, 0 = disable timer compare
 bit 0         0:      SELT1PR, 0 = use own period register
*/

/****************************/
/*** Setup Capture unit 1 ***/
/****************************/
	EvaRegs.CAPCONA.all = 0x0000;		// reset the capture units
/*
 bit 15        0:      CAPRES, 0 = reset the capture units and registers
*/

	EvaRegs.CAPCONA.all = 0xA280;		// Init CAPCONA register
/*
 bit 15        1:      CAPRES, 1 = no action
 bit 14-13     01:     CAP12EN, 01 = enable CAP1 and CAP2, QEP disabled
 bit 12        0:      CAP3EN, 0 = disable CAP3
 bit 11        0:      reserved
 bit 10        0:      CAP3TSEL, CAP3 uses:          0=timer2, 1=timer1
 bit 9         1:      CAP12TSEL, CAP1 and CAP2 use: 0=timer2, 1=timer1
 bit 8         0:      CAP3TOADC, 0 = CAP3 does not start ADC
 bit 7-6       10:     CAP1EDGE, 10 = CAP1 detects falling edges
 bit 5-4       00:     CAP2EDGE, 00 = CAP2 no detection
 bit 3-2       00:     CAP3EDGE, 00 = CAP3 no detection
 bit 1-0       00:     reserved
*/