simple_n.cpp

simulation routing in wsn

	// processor
	modtype = findModuleType( "proce" );
	check_modtype( modtype, "proce" );
	cModule *processor_mod;

	// an empty actual machine list for the next module
	par = new cPar();
	*par = mod->machinePar("default");
	machines.add( par );
	check_error(); check_memory();

	// module creation:
	islocal = simulation.netInterface()==NULL ||
	          simulation.netInterface()->isLocalMachineIn( machines );
	processor_mod = modtype->create( "processor", mod, islocal);
	check_error(); check_memory();

	// set machine list:
	processor_mod->setMachinePar( "default", ((cPar *)machines[0])->stringValue() );
	check_error(); check_memory();

	// 'parameters:' section
	par = &mod->ancestorPar( "nodeID" );
	check_anc_param(par,"nodeID","node");
	value.cancelRedirection();
	value = *par;
	par = &(processor_mod->par("nodeID"));
	check_param(par, "nodeID");
	*par = value;

	par = &mod->ancestorPar( "num_node" );
	check_anc_param(par,"num_node","node");
	value.cancelRedirection();
	value = *par;
	par = &(processor_mod->par("num_node"));
	check_param(par, "num_node");
	*par = value;

	par = &mod->ancestorPar( "convert" );
	check_anc_param(par,"convert","node");
	value.cancelRedirection();
	value = *par;
	par = &(processor_mod->par("convert"));
	check_param(par, "convert");
	*par = value;

	par = &mod->ancestorPar( "nwavelength" );
	check_anc_param(par,"nwavelength","node");
	value.cancelRedirection();
	value = *par;
	par = &(processor_mod->par("nwavelength"));
	check_param(par, "nwavelength");
	*par = value;

	n = processor_mod->params();
	for(k=0;k<n;k++)
	   if(processor_mod->par(k).isInput())
	      {processor_mod->par(k).read();check_error();}

	processor_mod->setDisplayString(dispSUBMOD, "p=92,196;b=72,40" );

	// build function call:
	processor_mod->buildInside();
	machines.clear();

	// transfer
	modtype = findModuleType( "trans" );
	check_modtype( modtype, "trans" );
	cModule *transfer_mod;

	// an empty actual machine list for the next module
	par = new cPar();
	*par = mod->machinePar("default");
	machines.add( par );
	check_error(); check_memory();

	// module creation:
	islocal = simulation.netInterface()==NULL ||
	          simulation.netInterface()->isLocalMachineIn( machines );
	transfer_mod = modtype->create( "transfer", mod, islocal);
	check_error(); check_memory();

	// set machine list:
	transfer_mod->setMachinePar( "default", ((cPar *)machines[0])->stringValue() );
	check_error(); check_memory();

	// 'parameters:' section
	par = &mod->ancestorPar( "nodeID" );
	check_anc_param(par,"nodeID","node");
	value.cancelRedirection();
	value = *par;
	par = &(transfer_mod->par("nodeID"));
	check_param(par, "nodeID");
	*par = value;

	par = &mod->ancestorPar( "num_node" );
	check_anc_param(par,"num_node","node");
	value.cancelRedirection();
	value = *par;
	par = &(transfer_mod->par("num_node"));
	check_param(par, "num_node");
	*par = value;

	par = &mod->ancestorPar( "convert" );
	check_anc_param(par,"convert","node");
	value.cancelRedirection();
	value = *par;
	par = &(transfer_mod->par("convert"));
	check_param(par, "convert");
	*par = value;

	par = &mod->ancestorPar( "nwavelength" );
	check_anc_param(par,"nwavelength","node");
	value.cancelRedirection();
	value = *par;
	par = &(transfer_mod->par("nwavelength"));
	check_param(par, "nwavelength");
	*par = value;

	n = transfer_mod->params();
	for(k=0;k<n;k++)
	   if(transfer_mod->par(k).isInput())
	      {transfer_mod->par(k).read();check_error();}

	// 'gatesizes:' section
	n = mod->par( "num_node" );
	check_gate_count( n, "transfer","tout","node");
	transfer_mod->setGateSize("tout", n );

	transfer_mod->setDisplayString(dispSUBMOD, "p=272,196;b=64,40" );

	// build function call:
	transfer_mod->buildInside();
	machines.clear();

	// Connections:
	cLinkType *link_p;
	cPar *delay_p, *error_p, *datarate_p;
	int gateL, gateR;
	long mod_nr_L, mod_nr_R, gate_nr_L, gate_nr_R;

	do_this_block = true; // no "if" condition
	if (do_this_block) // "if" in NED
	{
	gateL = receiver_mod->findGate( "rout" );
	check_gate( gateL, "receiver", "rout" );

	gateR = processor_mod->findGate( "pin" );
	check_gate( gateR, "processor", "pin" );

	connect (receiver_mod, gateL,
	         NULL,
	         processor_mod, gateR);

	check_error(); check_memory();
	} // end-if


	do_this_block = true; // no "if" condition
	if (do_this_block) // "if" in NED
	{
	gateL = processor_mod->findGate( "pout" );
	check_gate( gateL, "processor", "pout" );

	gateR = transfer_mod->findGate( "tinpro" );
	check_gate( gateR, "transfer", "tinpro" );

	connect (processor_mod, gateL,
	         NULL,
	         transfer_mod, gateR);

	check_error(); check_memory();
	} // end-if


	do_this_block = true; // no "if" condition
	if (do_this_block) // "if" in NED
	{
	gateL = generator_mod->findGate( "gout" );
	check_gate( gateL, "generator", "gout" );

	gateR = transfer_mod->findGate( "tingen" );
	check_gate( gateR, "transfer", "tingen" );

	connect (generator_mod, gateL,
	         NULL,
	         transfer_mod, gateR);

	check_error(); check_memory();
	} // end-if

	{
		// for i loop:
		long i_index;

		long i_begin = 0;
		expr_tab = new cPar::ExprElem[3]; k=0;
		expr_tab[k++] = mod->par( "num_node" );
		expr_tab[k++] = 1;
		expr_tab[k++] = '-';
		value.cancelRedirection();
		value.setDoubleValue(expr_tab,k);
		long i_end = value;
		check_loop_bounds(i_begin, i_end, "node");
		for (i_index=i_begin; i_index<=i_end; i_index++)
		{

			do_this_block = true; // no "if" condition
			if (do_this_block) // "if" in NED
			{
			gate_nr_L = i_index;
			gateL = transfer_mod->findGate( "tout", gate_nr_L );
			check_gate( gateL, "transfer", indexedname(b1,"tout",gate_nr_L) );

			gate_nr_R = i_index;
			gateR = mod->findGate( "nout", gate_nr_R );
			check_gate( gateR, "", indexedname(b1,"nout",gate_nr_R) );

			connect (transfer_mod, gateL,
			         NULL,
			         mod, gateR);

			check_error(); check_memory();
			} // end-if

		} // end for i

	}

	{
		// for i loop:
		long i_index;

		long i_begin = 0;
		expr_tab = new cPar::ExprElem[3]; k=0;
		expr_tab[k++] = mod->par( "num_node" );
		expr_tab[k++] = 1;
		expr_tab[k++] = '-';
		value.cancelRedirection();
		value.setDoubleValue(expr_tab,k);
		long i_end = value;
		check_loop_bounds(i_begin, i_end, "node");
		for (i_index=i_begin; i_index<=i_end; i_index++)
		{

			do_this_block = true; // no "if" condition
			if (do_this_block) // "if" in NED
			{
			gate_nr_L = i_index;
			gateL = receiver_mod->findGate( "rin", gate_nr_L );
			check_gate( gateL, "receiver", indexedname(b1,"rin",gate_nr_L) );

			gate_nr_R = i_index;
			gateR = mod->findGate( "nin", gate_nr_R );
			check_gate( gateR, "", indexedname(b1,"nin",gate_nr_R) );

			connect (mod, gateR,
			         NULL,
			         receiver_mod, gateL);

			check_error(); check_memory();
			} // end-if

		} // end for i

	}

	mod->setDisplayString(dispENCLOSINGMOD, "p=18,10;b=356,276" );

	check_error(); check_memory();
}