prev_cmp_jtag_logic.tan.qmsg

特权制作的USB-Blaster全部相关资料

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } } { "c:/altera/90/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register ioshifter\[7\] register state\[1\] 120.55 MHz 8.295 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 120.55 MHz between source register \"ioshifter\[7\]\" and destination register \"state\[1\]\" (period= 8.295 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.586 ns + Longest register register " "Info: + Longest register to register delay is 7.586 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ioshifter\[7\] 1 REG LC_X7_Y4_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y4_N0; Fanout = 4; REG Node = 'ioshifter\[7\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { ioshifter[7] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.795 ns) + CELL(0.914 ns) 3.709 ns Mux0~2 2 COMB LC_X5_Y2_N3 1 " "Info: 2: + IC(2.795 ns) + CELL(0.914 ns) = 3.709 ns; Loc. = LC_X5_Y2_N3; Fanout = 1; COMB Node = 'Mux0~2'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.709 ns" { ioshifter[7] Mux0~2 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.214 ns Mux0~3 3 COMB LC_X5_Y2_N4 1 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 4.214 ns; Loc. = LC_X5_Y2_N4; Fanout = 1; COMB Node = 'Mux0~3'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Mux0~2 Mux0~3 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.200 ns) 4.948 ns Mux2~0 4 COMB LC_X5_Y2_N5 1 " "Info: 4: + IC(0.534 ns) + CELL(0.200 ns) = 4.948 ns; Loc. = LC_X5_Y2_N5; Fanout = 1; COMB Node = 'Mux2~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.734 ns" { Mux0~3 Mux2~0 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.834 ns) + CELL(0.804 ns) 7.586 ns state\[1\] 5 REG LC_X6_Y3_N3 21 " "Info: 5: + IC(1.834 ns) + CELL(0.804 ns) = 7.586 ns; Loc. = LC_X6_Y3_N3; Fanout = 21; REG Node = 'state\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.638 ns" { Mux2~0 state[1] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.118 ns ( 27.92 % ) " "Info: Total cell delay = 2.118 ns ( 27.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.468 ns ( 72.08 % ) " "Info: Total interconnect delay = 5.468 ns ( 72.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.586 ns" { ioshifter[7] Mux0~2 Mux0~3 Mux2~0 state[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.586 ns" { ioshifter[7] {} Mux0~2 {} Mux0~3 {} Mux2~0 {} state[1] {} } { 0.000ns 2.795ns 0.305ns 0.534ns 1.834ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 47 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 47; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns state\[1\] 2 REG LC_X6_Y3_N3 21 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y3_N3; Fanout = 21; REG Node = 'state\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK state[1] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK state[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} state[1] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 47 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 47; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns ioshifter\[7\] 2 REG LC_X7_Y4_N0 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y4_N0; Fanout = 4; REG Node = 'ioshifter\[7\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK ioshifter[7] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 58 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK ioshifter[7] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} ioshifter[7] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK state[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} state[1] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK ioshifter[7] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} ioshifter[7] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 58 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.586 ns" { ioshifter[7] Mux0~2 Mux0~3 Mux2~0 state[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.586 ns" { ioshifter[7] {} Mux0~2 {} Mux0~3 {} Mux2~0 {} state[1] {} } { 0.000ns 2.795ns 0.305ns 0.534ns 1.834ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.804ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK state[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} state[1] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK ioshifter[7] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} ioshifter[7] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "state\[0\] nTXE CLK 4.193 ns register " "Info: tsu for register \"state\[0\]\" (data pin = \"nTXE\", clock pin = \"CLK\") is 4.193 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.208 ns + Longest pin register " "Info: + Longest pin to register delay is 7.208 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns nTXE 1 PIN PIN_62 2 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_62; Fanout = 2; PIN Node = 'nTXE'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { nTXE } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.018 ns) + CELL(0.914 ns) 4.095 ns Mux0~0 2 COMB LC_X5_Y2_N7 2 " "Info: 2: + IC(2.018 ns) + CELL(0.914 ns) = 4.095 ns; Loc. = LC_X5_Y2_N7; Fanout = 2; COMB Node = 'Mux0~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.932 ns" { nTXE Mux0~0 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.772 ns) + CELL(0.511 ns) 5.378 ns Mux0~7 3 COMB LC_X5_Y2_N0 1 " "Info: 3: + IC(0.772 ns) + CELL(0.511 ns) = 5.378 ns; Loc. = LC_X5_Y2_N0; Fanout = 1; COMB Node = 'Mux0~7'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { Mux0~0 Mux0~7 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.883 ns Mux3~0 4 COMB LC_X5_Y2_N1 1 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.883 ns; Loc. = LC_X5_Y2_N1; Fanout = 1; COMB Node = 'Mux3~0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Mux0~7 Mux3~0 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.734 ns) + CELL(0.591 ns) 7.208 ns state\[0\] 5 REG LC_X5_Y2_N8 21 " "Info: 5: + IC(0.734 ns) + CELL(0.591 ns) = 7.208 ns; Loc. = LC_X5_Y2_N8; Fanout = 21; REG Node = 'state\[0\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "1.325 ns" { Mux3~0 state[0] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.379 ns ( 46.88 % ) " "Info: Total cell delay = 3.379 ns ( 46.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.829 ns ( 53.12 % ) " "Info: Total interconnect delay = 3.829 ns ( 53.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.208 ns" { nTXE Mux0~0 Mux0~7 Mux3~0 state[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.208 ns" { nTXE {} nTXE~combout {} Mux0~0 {} Mux0~7 {} Mux3~0 {} state[0] {} } { 0.000ns 0.000ns 2.018ns 0.772ns 0.305ns 0.734ns } { 0.000ns 1.163ns 0.914ns 0.511ns 0.200ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 47 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 47; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns state\[0\] 2 REG LC_X5_Y2_N8 21 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N8; Fanout = 21; REG Node = 'state\[0\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK state[0] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK state[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} state[0] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "7.208 ns" { nTXE Mux0~0 Mux0~7 Mux3~0 state[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "7.208 ns" { nTXE {} nTXE~combout {} Mux0~0 {} Mux0~7 {} Mux3~0 {} state[0] {} } { 0.000ns 0.000ns 2.018ns 0.772ns 0.305ns 0.734ns } { 0.000ns 1.163ns 0.914ns 0.511ns 0.200ns 0.591ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK state[0] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} state[0] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK D\[1\] D\[1\]~reg0 8.980 ns register " "Info: tco from clock \"CLK\" to destination pin \"D\[1\]\" through register \"D\[1\]~reg0\" is 8.980 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 47 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 47; CLK Node = 'CLK'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns D\[1\]~reg0 2 REG LC_X2_Y3_N8 1 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y3_N8; Fanout = 1; REG Node = 'D\[1\]~reg0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { CLK D[1]~reg0 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK D[1]~reg0 } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} D[1]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.256 ns + Longest register pin " "Info: + Longest register to pin delay is 5.256 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns D\[1\]~reg0 1 REG LC_X2_Y3_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y3_N8; Fanout = 1; REG Node = 'D\[1\]~reg0'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[1]~reg0 } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.934 ns) + CELL(2.322 ns) 5.256 ns D\[1\] 2 PIN PIN_75 0 " "Info: 2: + IC(2.934 ns) + CELL(2.322 ns) = 5.256 ns; Loc. = PIN_75; Fanout = 0; PIN Node = 'D\[1\]'" {  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.256 ns" { D[1]~reg0 D[1] } "NODE_NAME" } } { "jtag_logic.vhd" "" { Text "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.vhd" 159 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 44.18 % ) " "Info: Total cell delay = 2.322 ns ( 44.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.934 ns ( 55.82 % ) " "Info: Total interconnect delay = 2.934 ns ( 55.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.256 ns" { D[1]~reg0 D[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.256 ns" { D[1]~reg0 {} D[1] {} } { 0.000ns 2.934ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { CLK D[1]~reg0 } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { CLK {} CLK~combout {} D[1]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "5.256 ns" { D[1]~reg0 D[1] } "NODE_NAME" } } { "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90/quartus/bin/Technology_Viewer.qrui" "5.256 ns" { D[1]~reg0 {} D[1] {} } { 0.000ns 2.934ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}