📄 jtag_logic.fit.rpt
字号:
Fitter report for jtag_logic
Wed Sep 02 10:17:33 2009
Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
5. Pin-Out File
6. Fitter Resource Usage Summary
7. Input Pins
8. Output Pins
9. Bidir Pins
10. I/O Bank Usage
11. All Package Pins
12. Output Pin Default Load For Reported TCO
13. Fitter Resource Utilization by Entity
14. Delay Chain Summary
15. Control Signals
16. Global & Other Fast Signals
17. Non-Global High Fan-Out Signals
18. Interconnect Usage Summary
19. LAB Logic Elements
20. LAB-wide Signals
21. LAB Signals Sourced
22. LAB Signals Sourced Out
23. LAB Distinct Inputs
24. Fitter Device Options
25. Estimated Delay Added for Hold Timing
26. Advanced Data - General
27. Advanced Data - Placement Preparation
28. Advanced Data - Placement
29. Advanced Data - Routing
30. Fitter Messages
31. Fitter Suppressed Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+------------------------------------------+
; Fitter Status ; Successful - Wed Sep 02 10:17:33 2009 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
; Revision Name ; jtag_logic ;
; Top-level Entity Name ; jtag_logic ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 75 / 240 ( 31 % ) ;
; Total pins ; 21 / 80 ( 26 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EPM240T100C5 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Device I/O Standard ; 3.3-V LVTTL ; ;
; Use smart compilation ; Off ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Always Enable Input Buffers ; Off ; Off ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing ; Off ; Off ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize Timing for ECOs ; Off ; Off ;
; Regenerate full fit report during ECO compiles ; Off ; Off ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Delay Chains ; On ; On ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Auto ; Auto ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Stop After Congestion Map Generation ; Off ; Off ;
; Save Intermediate Fitting Results ; Off ; Off ;
; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; 1 processor ; 100.0% ;
; 2 processors ; < 0.1% ;
+----------------------------+-------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/xjwjj/USB blaster/SF-USBblaster V2.0 (090902)/verilog_prj/jtag_logic.pin.
+-----------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+-------------------+
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