jtag_logic.qsf

特权制作的USB-Blaster全部相关资料

# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		jtag_logic_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY jtag_logic
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:44:53  MAY 04, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name VHDL_FILE jtag_logic.vhd
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name MISC_FILE "E:/Personal/USB blaster/verilog_prj/jtag_logic.dpf"
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_12 -to CLK
set_location_assignment PIN_74 -to D[7]
set_location_assignment PIN_71 -to D[3]
set_location_assignment PIN_72 -to D[6]
set_location_assignment PIN_73 -to D[5]
set_location_assignment PIN_75 -to D[1]
set_location_assignment PIN_76 -to D[2]
set_location_assignment PIN_77 -to D[4]
set_location_assignment PIN_78 -to D[0]
set_location_assignment PIN_67 -to nRD
set_location_assignment PIN_66 -to WR
set_location_assignment PIN_64 -to nRXF
set_location_assignment PIN_62 -to nTXE
set_location_assignment PIN_15 -to B_TCK
set_location_assignment PIN_16 -to B_TDO
set_location_assignment PIN_18 -to B_TMS
set_location_assignment PIN_21 -to B_TDI
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name MISC_FILE "E:/xjwjj/USB blaster/verilog_prj/jtag_logic.dpf"
set_location_assignment PIN_17 -to B_NCE
set_location_assignment PIN_19 -to B_NCS
set_location_assignment PIN_20 -to B_ASDO
set_global_assignment -name MISC_FILE "E:/xjwjj/USB blaster/SF-USBblaster V2.0 (090902)/verilog_prj/jtag_logic.dpf"