jtag_logic.tan.rpt

特权制作的USB-Blaster全部相关资料

+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To    ; From Clock ;
+-------+--------------+------------+------------+-------+------------+
; N/A   ; None         ; 8.867 ns   ; D[4]~reg0  ; D[4]  ; CLK        ;
; N/A   ; None         ; 8.811 ns   ; D[2]~reg0  ; D[2]  ; CLK        ;
; N/A   ; None         ; 8.770 ns   ; D[3]~reg0  ; D[3]  ; CLK        ;
; N/A   ; None         ; 8.765 ns   ; D[1]~reg0  ; D[1]  ; CLK        ;
; N/A   ; None         ; 8.757 ns   ; D[5]~reg0  ; D[5]  ; CLK        ;
; N/A   ; None         ; 8.727 ns   ; B_TDI~reg0 ; B_TDI ; CLK        ;
; N/A   ; None         ; 8.711 ns   ; B_NCE~reg0 ; B_NCE ; CLK        ;
; N/A   ; None         ; 8.649 ns   ; WR~reg0    ; WR    ; CLK        ;
; N/A   ; None         ; 8.597 ns   ; nRD~reg0   ; nRD   ; CLK        ;
; N/A   ; None         ; 8.469 ns   ; B_OE~reg0  ; B_OE  ; CLK        ;
; N/A   ; None         ; 8.106 ns   ; D[0]~reg0  ; D[0]  ; CLK        ;
; N/A   ; None         ; 8.020 ns   ; B_TCK~reg0 ; B_TCK ; CLK        ;
; N/A   ; None         ; 8.005 ns   ; B_NCS~reg0 ; B_NCS ; CLK        ;
; N/A   ; None         ; 7.993 ns   ; D[7]~reg0  ; D[7]  ; CLK        ;
; N/A   ; None         ; 7.954 ns   ; B_TMS~reg0 ; B_TMS ; CLK        ;
; N/A   ; None         ; 7.950 ns   ; D[6]~reg0  ; D[6]  ; CLK        ;
; N/A   ; None         ; 7.873 ns   ; D[3]~en    ; D[3]  ; CLK        ;
; N/A   ; None         ; 7.491 ns   ; D[7]~en    ; D[7]  ; CLK        ;
; N/A   ; None         ; 7.456 ns   ; D[4]~en    ; D[4]  ; CLK        ;
; N/A   ; None         ; 7.444 ns   ; D[5]~en    ; D[5]  ; CLK        ;
; N/A   ; None         ; 7.379 ns   ; D[1]~en    ; D[1]  ; CLK        ;
; N/A   ; None         ; 7.238 ns   ; D[0]~en    ; D[0]  ; CLK        ;
; N/A   ; None         ; 7.223 ns   ; D[2]~en    ; D[2]  ; CLK        ;
; N/A   ; None         ; 6.805 ns   ; D[6]~en    ; D[6]  ; CLK        ;
+-------+--------------+------------+------------+-------+------------+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+--------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To           ; To Clock ;
+---------------+-------------+-----------+--------+--------------+----------+
; N/A           ; None        ; -1.298 ns ; D[2]   ; ioshifter[2] ; CLK      ;
; N/A           ; None        ; -1.309 ns ; D[4]   ; ioshifter[4] ; CLK      ;
; N/A           ; None        ; -1.383 ns ; D[5]   ; ioshifter[5] ; CLK      ;
; N/A           ; None        ; -1.422 ns ; D[3]   ; ioshifter[3] ; CLK      ;
; N/A           ; None        ; -1.555 ns ; D[7]   ; ioshifter[7] ; CLK      ;
; N/A           ; None        ; -1.569 ns ; D[6]   ; ioshifter[6] ; CLK      ;
; N/A           ; None        ; -1.702 ns ; B_TDO  ; ioshifter[0] ; CLK      ;
; N/A           ; None        ; -1.889 ns ; B_ASDO ; carry        ; CLK      ;
; N/A           ; None        ; -1.901 ns ; D[0]   ; ioshifter[0] ; CLK      ;
; N/A           ; None        ; -1.929 ns ; D[1]   ; ioshifter[1] ; CLK      ;
; N/A           ; None        ; -1.974 ns ; nTXE   ; state[2]     ; CLK      ;
; N/A           ; None        ; -2.262 ns ; B_TDO  ; carry        ; CLK      ;
; N/A           ; None        ; -2.287 ns ; B_ASDO ; ioshifter[1] ; CLK      ;
; N/A           ; None        ; -3.064 ns ; nTXE   ; state[0]     ; CLK      ;
; N/A           ; None        ; -3.437 ns ; nRXF   ; state[0]     ; CLK      ;
; N/A           ; None        ; -3.935 ns ; nTXE   ; state[1]     ; CLK      ;
+---------------+-------------+-----------+--------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
    Info: Processing started: Wed Sep 02 10:17:41 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jtag_logic -c jtag_logic
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 118.3 MHz between source register "ioshifter[7]" and destination register "state[1]" (period= 8.453 ns)
    Info: + Longest register to register delay is 7.744 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y4_N2; Fanout = 4; REG Node = 'ioshifter[7]'
        Info: 2: + IC(3.221 ns) + CELL(0.511 ns) = 3.732 ns; Loc. = LC_X4_Y3_N1; Fanout = 1; COMB Node = 'Mux0~2'
        Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 4.237 ns; Loc. = LC_X4_Y3_N2; Fanout = 1; COMB Node = 'Mux0~3'
        Info: 4: + IC(0.720 ns) + CELL(0.200 ns) = 5.157 ns; Loc. = LC_X4_Y3_N0; Fanout = 1; COMB Node = 'Mux2~0'
        Info: 5: + IC(1.783 ns) + CELL(0.804 ns) = 7.744 ns; Loc. = LC_X4_Y2_N0; Fanout = 21; REG Node = 'state[1]'
        Info: Total cell delay = 1.715 ns ( 22.15 % )
        Info: Total interconnect delay = 6.029 ns ( 77.85 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 47; CLK Node = 'CLK'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y2_N0; Fanout = 21; REG Node = 'state[1]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "CLK" to source register is 3.348 ns
            Info: 1: + I