📄 dds.map.rpt
字号:
; -- normal mode ; 11 ;
; -- arithmetic mode ; 9 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 20 ;
; Total logic cells in carry chains ; 10 ;
; I/O pins ; 21 ;
; Total memory bits ; 10240 ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 30 ;
; Total fan-out ; 179 ;
; Average fan-out ; 3.51 ;
+---------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+
; |DDS_VHDL ; 20 (0) ; 20 ; 10240 ; 0 ; 0 ; 0 ; 0 ; 21 ; 0 ; 0 (0) ; 10 (0) ; 10 (0) ; 10 (0) ; 0 (0) ; |DDS_VHDL ;
; |REG10B:u2| ; 10 (10) ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 10 (10) ; 10 (10) ; 0 (0) ; |DDS_VHDL|REG10B:u2 ;
; |REG10B:u3| ; 10 (10) ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 10 (10) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|REG10B:u3 ;
; |lpm_rom0:u6| ; 0 (0) ; 0 ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|lpm_rom0:u6 ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|lpm_rom0:u6|altsyncram:altsyncram_component ;
; |altsyncram_l5s:auto_generated| ; 0 (0) ; 0 ; 10240 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |DDS_VHDL|lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated ;
+------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+--------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+------------+
; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 1024 ; 10 ; -- ; -- ; 10240 ; sinsin.mif ;
+--------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 20 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------+
; Source assignments for lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------+
; Assignment ; Value ; from ; to ;
+---------------------------------+--------------------+------+------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_rom0:u6|altsyncram:altsyncram_component ;
+------------------------------------+----------------+------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------+------------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 10 ; Integer ;
; WIDTHAD_A ; 10 ; Integer ;
; NUMWORDS_A ; 1024 ; Integer ;
; OUTDATA_REG_A ; CLOCK0 ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; sinsin.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Stratix ; Untyped ;
; CBXI_PARAMETER ; altsyncram_l5s ; Untyped ;
+------------------------------------+----------------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/yeping/桌面/DDS/DDS.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Mon May 28 15:59:35 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS
Info: Found 2 design units, including 1 entities, in source file DDS.vhd
Info: Found design unit 1: DDS_VHDL-one
Info: Found entity 1: DDS_VHDL
Info: Found 2 design units, including 1 entities, in source file REG10B.vhd
Info: Found design unit 1: REG10B-behav
Info: Found entity 1: REG10B
Info: Found 2 design units, including 1 entities, in source file ADDER10B.vhd
Info: Found design unit 1: ADDER10B-behav
Info: Found entity 1: ADDER10B
Info: Elaborating entity "DDS_VHDL" for the top level hierarchy
Info: Elaborating entity "ADDER10B" for hierarchy "ADDER10B:u1"
Info: Elaborating entity "REG10B" for hierarchy "REG10B:u2"
Warning: Using design file lpm_rom0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: lpm_rom0-SYN
Info: Found entity 1: lpm_rom0
Info: Elaborating entity "lpm_rom0" for hierarchy "lpm_rom0:u6"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom0:u6|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_l5s.tdf
Info: Found entity 1: altsyncram_l5s
Info: Elaborating entity "altsyncram_l5s" for hierarchy "lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated"
Info: Implemented 51 device resources after synthesis - the final resource count might be different
Info: Implemented 11 input pins
Info: Implemented 10 output pins
Info: Implemented 20 logic cells
Info: Implemented 10 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Processing ended: Mon May 28 15:59:37 2007
Info: Elapsed time: 00:00:03
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -