dds.map.qmsg

经过仿真验证的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 28 15:59:35 2007 " "Info: Processing started: Mon May 28 15:59:35 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DDS.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DDS_VHDL-one " "Info: Found design unit 1: DDS_VHDL-one" {  } { { "DDS.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DDS_VHDL " "Info: Found entity 1: DDS_VHDL" {  } { { "DDS.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG10B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG10B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG10B-behav " "Info: Found design unit 1: REG10B-behav" {  } { { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG10B " "Info: Found entity 1: REG10B" {  } { { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER10B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER10B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER10B-behav " "Info: Found design unit 1: ADDER10B-behav" {  } { { "ADDER10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/ADDER10B.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER10B " "Info: Found entity 1: ADDER10B" {  } { { "ADDER10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/ADDER10B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DDS_VHDL " "Info: Elaborating entity \"DDS_VHDL\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDER10B ADDER10B:u1 " "Info: Elaborating entity \"ADDER10B\" for hierarchy \"ADDER10B:u1\"" {  } { { "DDS.vhd" "u1" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 34 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG10B REG10B:u2 " "Info: Elaborating entity \"REG10B\" for hierarchy \"REG10B:u2\"" {  } { { "DDS.vhd" "u2" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 36 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom0.vhd 2 1 " "Warning: Using design file lpm_rom0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom0-SYN " "Info: Found design unit 1: lpm_rom0-SYN" {  } { { "lpm_rom0.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/lpm_rom0.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0 " "Info: Found entity 1: lpm_rom0" {  } { { "lpm_rom0.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/lpm_rom0.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0 lpm_rom0:u6 " "Info: Elaborating entity \"lpm_rom0\" for hierarchy \"lpm_rom0:u6\"" {  } { { "DDS.vhd" "u6" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 38 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom0:u6\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom0:u6\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.vhd" "altsyncram_component" { Text "C:/Documents and Settings/yeping/桌面/DDS/lpm_rom0.vhd" 80 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_l5s.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_l5s.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_l5s " "Info: Found entity 1: altsyncram_l5s" {  } { { "db/altsyncram_l5s.tdf" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/db/altsyncram_l5s.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_l5s lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated " "Info: Elaborating entity \"altsyncram_l5s\" for hierarchy \"lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "51 " "Info: Implemented 51 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "20 " "Info: Implemented 20 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "10 " "Info: Implemented 10 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 28 15:59:37 2007 " "Info: Processing ended: Mon May 28 15:59:37 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}