📄 dds.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK memory lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|ram_block1a3~porta_address_reg0 memory lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|q_a\[6\] 290.87 MHz 3.438 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 290.87 MHz between source memory \"lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|ram_block1a3~porta_address_reg0\" and destination memory \"lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|q_a\[6\]\" (period= 3.438 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.875 ns + Longest memory memory " "Info: + Longest memory to memory delay is 2.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|ram_block1a3~porta_address_reg0 1 MEM M4K_X15_Y22 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X15_Y22; Fanout = 2; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|ram_block1a3~porta_address_reg0'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_l5s.tdf" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/db/altsyncram_l5s.tdf" 103 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.875 ns) 2.875 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|q_a\[6\] 2 MEM M4K_X15_Y22 1 " "Info: 2: + IC(0.000 ns) + CELL(2.875 ns) = 2.875 ns; Loc. = M4K_X15_Y22; Fanout = 1; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|q_a\[6\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.875 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "db/altsyncram_l5s.tdf" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/db/altsyncram_l5s.tdf" 40 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.875 ns ( 100.00 % ) " "Info: Total cell delay = 2.875 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.875 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.875 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] } { 0.000ns 0.000ns } { 0.000ns 2.875ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.012 ns - Smallest " "Info: - Smallest clock skew is -0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.774 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 2.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 60 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 60; CLK Node = 'CLK'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.549 ns) + CELL(0.500 ns) 2.774 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|q_a\[6\] 2 MEM M4K_X15_Y22 1 " "Info: 2: + IC(1.549 ns) + CELL(0.500 ns) = 2.774 ns; Loc. = M4K_X15_Y22; Fanout = 1; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|q_a\[6\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.049 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "db/altsyncram_l5s.tdf" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/db/altsyncram_l5s.tdf" 40 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.225 ns ( 44.16 % ) " "Info: Total cell delay = 1.225 ns ( 44.16 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.549 ns ( 55.84 % ) " "Info: Total interconnect delay = 1.549 ns ( 55.84 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.774 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.774 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] } { 0.000ns 0.000ns 1.549ns } { 0.000ns 0.725ns 0.500ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.786 ns - Longest memory " "Info: - Longest clock path from clock \"CLK\" to source memory is 2.786 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 60 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 60; CLK Node = 'CLK'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.549 ns) + CELL(0.512 ns) 2.786 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|ram_block1a3~porta_address_reg0 2 MEM M4K_X15_Y22 2 " "Info: 2: + IC(1.549 ns) + CELL(0.512 ns) = 2.786 ns; Loc. = M4K_X15_Y22; Fanout = 2; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|ram_block1a3~porta_address_reg0'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.061 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_l5s.tdf" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/db/altsyncram_l5s.tdf" 103 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.237 ns ( 44.40 % ) " "Info: Total cell delay = 1.237 ns ( 44.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.549 ns ( 55.60 % ) " "Info: Total interconnect delay = 1.549 ns ( 55.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.786 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.786 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 } { 0.000ns 0.000ns 1.549ns } { 0.000ns 0.725ns 0.512ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.774 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.774 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] } { 0.000ns 0.000ns 1.549ns } { 0.000ns 0.725ns 0.500ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.786 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.786 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 } { 0.000ns 0.000ns 1.549ns } { 0.000ns 0.725ns 0.512ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns + " "Info: + Micro clock to output delay of source is 0.420 ns" { } { { "db/altsyncram_l5s.tdf" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/db/altsyncram_l5s.tdf" 103 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.131 ns + " "Info: + Micro setup delay of destination is 0.131 ns" { } { { "db/altsyncram_l5s.tdf" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/db/altsyncram_l5s.tdf" 40 2 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.875 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.875 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] } { 0.000ns 0.000ns } { 0.000ns 2.875ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.774 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.774 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] } { 0.000ns 0.000ns 1.549ns } { 0.000ns 0.725ns 0.500ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.786 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.786 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|ram_block1a3~porta_address_reg0 } { 0.000ns 0.000ns 1.549ns } { 0.000ns 0.725ns 0.512ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "REG10B:u2\|DOUT\[5\] FWORD\[0\] CLK 4.235 ns register " "Info: tsu for register \"REG10B:u2\|DOUT\[5\]\" (data pin = \"FWORD\[0\]\", clock pin = \"CLK\") is 4.235 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.041 ns + Longest pin register " "Info: + Longest pin to register delay is 7.041 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns FWORD\[0\] 1 PIN PIN_W15 3 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W15; Fanout = 3; PIN Node = 'FWORD\[0\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "" { FWORD[0] } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.627 ns) + CELL(0.451 ns) 6.165 ns REG10B:u2\|DOUT\[0\]~71COUT1_111 2 COMB LC_X18_Y22_N0 2 " "Info: 2: + IC(4.627 ns) + CELL(0.451 ns) = 6.165 ns; Loc. = LC_X18_Y22_N0; Fanout = 2; COMB Node = 'REG10B:u2\|DOUT\[0\]~71COUT1_111'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "5.078 ns" { FWORD[0] REG10B:u2|DOUT[0]~71COUT1_111 } "NODE_NAME" } "" } } { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 6.225 ns REG10B:u2\|DOUT\[1\]~75COUT1_112 3 COMB LC_X18_Y22_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 6.225 ns; Loc. = LC_X18_Y22_N1; Fanout = 2; COMB Node = 'REG10B:u2\|DOUT\[1\]~75COUT1_112'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "0.060 ns" { REG10B:u2|DOUT[0]~71COUT1_111 REG10B:u2|DOUT[1]~75COUT1_112 } "NODE_NAME" } "" } } { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 6.285 ns REG10B:u2\|DOUT\[2\]~79COUT1_113 4 COMB LC_X18_Y22_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 6.285 ns; Loc. = LC_X18_Y22_N2; Fanout = 2; COMB Node = 'REG10B:u2\|DOUT\[2\]~79COUT1_113'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "0.060 ns" { REG10B:u2|DOUT[1]~75COUT1_112 REG10B:u2|DOUT[2]~79COUT1_113 } "NODE_NAME" } "" } } { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 6.345 ns REG10B:u2\|DOUT\[3\]~83COUT1_114 5 COMB LC_X18_Y22_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 6.345 ns; Loc. = LC_X18_Y22_N3; Fanout = 2; COMB Node = 'REG10B:u2\|DOUT\[3\]~83COUT1_114'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "0.060 ns" { REG10B:u2|DOUT[2]~79COUT1_113 REG10B:u2|DOUT[3]~83COUT1_114 } "NODE_NAME" } "" } } { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.118 ns) 6.463 ns REG10B:u2\|DOUT\[4\]~87 6 COMB LC_X18_Y22_N4 5 " "Info: 6: + IC(0.000 ns) + CELL(0.118 ns) = 6.463 ns; Loc. = LC_X18_Y22_N4; Fanout = 5; COMB Node = 'REG10B:u2\|DOUT\[4\]~87'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "0.118 ns" { REG10B:u2|DOUT[3]~83COUT1_114 REG10B:u2|DOUT[4]~87 } "NODE_NAME" } "" } } { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.578 ns) 7.041 ns REG10B:u2\|DOUT\[5\] 7 REG LC_X18_Y22_N5 4 " "Info: 7: + IC(0.000 ns) + CELL(0.578 ns) = 7.041 ns; Loc. = LC_X18_Y22_N5; Fanout = 4; REG Node = 'REG10B:u2\|DOUT\[5\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "0.578 ns" { REG10B:u2|DOUT[4]~87 REG10B:u2|DOUT[5] } "NODE_NAME" } "" } } { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.414 ns ( 34.28 % ) " "Info: Total cell delay = 2.414 ns ( 34.28 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.627 ns ( 65.72 % ) " "Info: Total interconnect delay = 4.627 ns ( 65.72 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "7.041 ns" { FWORD[0] REG10B:u2|DOUT[0]~71COUT1_111 REG10B:u2|DOUT[1]~75COUT1_112 REG10B:u2|DOUT[2]~79COUT1_113 REG10B:u2|DOUT[3]~83COUT1_114 REG10B:u2|DOUT[4]~87 REG10B:u2|DOUT[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.041 ns" { FWORD[0] FWORD[0]~out0 REG10B:u2|DOUT[0]~71COUT1_111 REG10B:u2|DOUT[1]~75COUT1_112 REG10B:u2|DOUT[2]~79COUT1_113 REG10B:u2|DOUT[3]~83COUT1_114 REG10B:u2|DOUT[4]~87 REG10B:u2|DOUT[5] } { 0.000ns 0.000ns 4.627ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.087ns 0.451ns 0.060ns 0.060ns 0.060ns 0.118ns 0.578ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 12 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.816 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 60 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 60; CLK Node = 'CLK'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.549 ns) + CELL(0.542 ns) 2.816 ns REG10B:u2\|DOUT\[5\] 2 REG LC_X18_Y22_N5 4 " "Info: 2: + IC(1.549 ns) + CELL(0.542 ns) = 2.816 ns; Loc. = LC_X18_Y22_N5; Fanout = 4; REG Node = 'REG10B:u2\|DOUT\[5\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.091 ns" { CLK REG10B:u2|DOUT[5] } "NODE_NAME" } "" } } { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.99 % ) " "Info: Total cell delay = 1.267 ns ( 44.99 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.549 ns ( 55.01 % ) " "Info: Total interconnect delay = 1.549 ns ( 55.01 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.816 ns" { CLK REG10B:u2|DOUT[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.816 ns" { CLK CLK~out0 REG10B:u2|DOUT[5] } { 0.000ns 0.000ns 1.549ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "7.041 ns" { FWORD[0] REG10B:u2|DOUT[0]~71COUT1_111 REG10B:u2|DOUT[1]~75COUT1_112 REG10B:u2|DOUT[2]~79COUT1_113 REG10B:u2|DOUT[3]~83COUT1_114 REG10B:u2|DOUT[4]~87 REG10B:u2|DOUT[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.041 ns" { FWORD[0] FWORD[0]~out0 REG10B:u2|DOUT[0]~71COUT1_111 REG10B:u2|DOUT[1]~75COUT1_112 REG10B:u2|DOUT[2]~79COUT1_113 REG10B:u2|DOUT[3]~83COUT1_114 REG10B:u2|DOUT[4]~87 REG10B:u2|DOUT[5] } { 0.000ns 0.000ns 4.627ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.087ns 0.451ns 0.060ns 0.060ns 0.060ns 0.118ns 0.578ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.816 ns" { CLK REG10B:u2|DOUT[5] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.816 ns" { CLK CLK~out0 REG10B:u2|DOUT[5] } { 0.000ns 0.000ns 1.549ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK FOUT\[7\] lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|q_a\[7\] 8.045 ns memory " "Info: tco from clock \"CLK\" to destination pin \"FOUT\[7\]\" through memory \"lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|q_a\[7\]\" is 8.045 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.784 ns + Longest memory " "Info: + Longest clock path from clock \"CLK\" to source memory is 2.784 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 60 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 60; CLK Node = 'CLK'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.559 ns) + CELL(0.500 ns) 2.784 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|q_a\[7\] 2 MEM M4K_X15_Y20 1 " "Info: 2: + IC(1.559 ns) + CELL(0.500 ns) = 2.784 ns; Loc. = M4K_X15_Y20; Fanout = 1; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|q_a\[7\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.059 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "db/altsyncram_l5s.tdf" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/db/altsyncram_l5s.tdf" 40 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.225 ns ( 44.00 % ) " "Info: Total cell delay = 1.225 ns ( 44.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.559 ns ( 56.00 % ) " "Info: Total interconnect delay = 1.559 ns ( 56.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.784 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.784 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7] } { 0.000ns 0.000ns 1.559ns } { 0.000ns 0.725ns 0.500ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns + " "Info: + Micro clock to output delay of source is 0.420 ns" { } { { "db/altsyncram_l5s.tdf" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/db/altsyncram_l5s.tdf" 40 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.841 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.841 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.071 ns lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|q_a\[7\] 1 MEM M4K_X15_Y20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.071 ns) = 0.071 ns; Loc. = M4K_X15_Y20; Fanout = 1; MEM Node = 'lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_l5s:auto_generated\|q_a\[7\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "db/altsyncram_l5s.tdf" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/db/altsyncram_l5s.tdf" 40 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.366 ns) + CELL(2.404 ns) 4.841 ns FOUT\[7\] 2 PIN PIN_V14 0 " "Info: 2: + IC(2.366 ns) + CELL(2.404 ns) = 4.841 ns; Loc. = PIN_V14; Fanout = 0; PIN Node = 'FOUT\[7\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "4.770 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7] FOUT[7] } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.475 ns ( 51.13 % ) " "Info: Total cell delay = 2.475 ns ( 51.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.366 ns ( 48.87 % ) " "Info: Total interconnect delay = 2.366 ns ( 48.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "4.841 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7] FOUT[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.841 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7] FOUT[7] } { 0.000ns 2.366ns } { 0.071ns 2.404ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.784 ns" { CLK lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.784 ns" { CLK CLK~out0 lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7] } { 0.000ns 0.000ns 1.559ns } { 0.000ns 0.725ns 0.500ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "4.841 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7] FOUT[7] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "4.841 ns" { lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7] FOUT[7] } { 0.000ns 2.366ns } { 0.071ns 2.404ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "REG10B:u2\|DOUT\[9\] FWORD\[9\] CLK -2.448 ns register " "Info: th for register \"REG10B:u2\|DOUT\[9\]\" (data pin = \"FWORD\[9\]\", clock pin = \"CLK\") is -2.448 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.816 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.816 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 60 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 60; CLK Node = 'CLK'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.549 ns) + CELL(0.542 ns) 2.816 ns REG10B:u2\|DOUT\[9\] 2 REG LC_X18_Y22_N9 2 " "Info: 2: + IC(1.549 ns) + CELL(0.542 ns) = 2.816 ns; Loc. = LC_X18_Y22_N9; Fanout = 2; REG Node = 'REG10B:u2\|DOUT\[9\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.091 ns" { CLK REG10B:u2|DOUT[9] } "NODE_NAME" } "" } } { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.99 % ) " "Info: Total cell delay = 1.267 ns ( 44.99 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.549 ns ( 55.01 % ) " "Info: Total interconnect delay = 1.549 ns ( 55.01 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.816 ns" { CLK REG10B:u2|DOUT[9] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.816 ns" { CLK CLK~out0 REG10B:u2|DOUT[9] } { 0.000ns 0.000ns 1.549ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 12 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.364 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.364 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns FWORD\[9\] 1 PIN PIN_C15 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C15; Fanout = 1; PIN Node = 'FWORD\[9\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "" { FWORD[9] } "NODE_NAME" } "" } } { "DDS.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/DDS.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.054 ns) + CELL(0.223 ns) 5.364 ns REG10B:u2\|DOUT\[9\] 2 REG LC_X18_Y22_N9 2 " "Info: 2: + IC(4.054 ns) + CELL(0.223 ns) = 5.364 ns; Loc. = LC_X18_Y22_N9; Fanout = 2; REG Node = 'REG10B:u2\|DOUT\[9\]'" { } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "4.277 ns" { FWORD[9] REG10B:u2|DOUT[9] } "NODE_NAME" } "" } } { "REG10B.vhd" "" { Text "C:/Documents and Settings/yeping/桌面/DDS/REG10B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.310 ns ( 24.42 % ) " "Info: Total cell delay = 1.310 ns ( 24.42 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.054 ns ( 75.58 % ) " "Info: Total interconnect delay = 4.054 ns ( 75.58 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "5.364 ns" { FWORD[9] REG10B:u2|DOUT[9] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.364 ns" { FWORD[9] FWORD[9]~out0 REG10B:u2|DOUT[9] } { 0.000ns 0.000ns 4.054ns } { 0.000ns 1.087ns 0.223ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "2.816 ns" { CLK REG10B:u2|DOUT[9] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "2.816 ns" { CLK CLK~out0 REG10B:u2|DOUT[9] } { 0.000ns 0.000ns 1.549ns } { 0.000ns 0.725ns 0.542ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "C:/Documents and Settings/yeping/桌面/DDS/db/DDS.quartus_db" { Floorplan "C:/Documents and Settings/yeping/桌面/DDS/" "" "5.364 ns" { FWORD[9] REG10B:u2|DOUT[9] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.364 ns" { FWORD[9] FWORD[9]~out0 REG10B:u2|DOUT[9] } { 0.000ns 0.000ns 4.054ns } { 0.000ns 1.087ns 0.223ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -