📄 dds.sim.rpt
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; |DDS_VHDL|REG10B:u2|DOUT[2] ; |DDS_VHDL|REG10B:u2|DOUT[2] ; regout ;
; |DDS_VHDL|REG10B:u2|DOUT[2] ; |DDS_VHDL|REG10B:u2|DOUT[2]~79 ; cout0 ;
; |DDS_VHDL|REG10B:u2|DOUT[2] ; |DDS_VHDL|REG10B:u2|DOUT[2]~79COUT1_113 ; cout1 ;
; |DDS_VHDL|REG10B:u2|DOUT[3] ; |DDS_VHDL|REG10B:u2|DOUT[3] ; regout ;
; |DDS_VHDL|REG10B:u2|DOUT[3] ; |DDS_VHDL|REG10B:u2|DOUT[3]~83 ; cout0 ;
; |DDS_VHDL|REG10B:u2|DOUT[3] ; |DDS_VHDL|REG10B:u2|DOUT[3]~83COUT1_114 ; cout1 ;
; |DDS_VHDL|REG10B:u2|DOUT[4] ; |DDS_VHDL|REG10B:u2|DOUT[4] ; regout ;
; |DDS_VHDL|REG10B:u2|DOUT[4] ; |DDS_VHDL|REG10B:u2|DOUT[4]~87 ; cout ;
; |DDS_VHDL|REG10B:u2|DOUT[5] ; |DDS_VHDL|REG10B:u2|DOUT[5] ; regout ;
; |DDS_VHDL|REG10B:u2|DOUT[5] ; |DDS_VHDL|REG10B:u2|DOUT[5]~91COUT1_115 ; cout1 ;
; |DDS_VHDL|REG10B:u2|DOUT[6] ; |DDS_VHDL|REG10B:u2|DOUT[6] ; regout ;
; |DDS_VHDL|REG10B:u2|DOUT[6] ; |DDS_VHDL|REG10B:u2|DOUT[6]~95COUT1_116 ; cout1 ;
; |DDS_VHDL|CLK ; |DDS_VHDL|CLK ; combout ;
; |DDS_VHDL|FOUT[0] ; |DDS_VHDL|FOUT[0] ; padio ;
; |DDS_VHDL|FOUT[1] ; |DDS_VHDL|FOUT[1] ; padio ;
; |DDS_VHDL|FOUT[2] ; |DDS_VHDL|FOUT[2] ; padio ;
; |DDS_VHDL|FOUT[3] ; |DDS_VHDL|FOUT[3] ; padio ;
; |DDS_VHDL|FOUT[4] ; |DDS_VHDL|FOUT[4] ; padio ;
; |DDS_VHDL|FOUT[5] ; |DDS_VHDL|FOUT[5] ; padio ;
; |DDS_VHDL|FOUT[6] ; |DDS_VHDL|FOUT[6] ; padio ;
; |DDS_VHDL|FOUT[7] ; |DDS_VHDL|FOUT[7] ; padio ;
; |DDS_VHDL|FOUT[8] ; |DDS_VHDL|FOUT[8] ; padio ;
; |DDS_VHDL|FOUT[9] ; |DDS_VHDL|FOUT[9] ; padio ;
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+-----------------------------+------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------------------------+------------------------------------------+------------------+
; |DDS_VHDL|REG10B:u3|DOUT[0] ; |DDS_VHDL|REG10B:u3|DOUT[0] ; regout ;
; |DDS_VHDL|REG10B:u3|DOUT[8] ; |DDS_VHDL|REG10B:u3|DOUT[8] ; regout ;
; |DDS_VHDL|REG10B:u3|DOUT[9] ; |DDS_VHDL|REG10B:u3|DOUT[9] ; regout ;
; |DDS_VHDL|REG10B:u2|DOUT[0] ; |DDS_VHDL|REG10B:u2|DOUT[0] ; regout ;
; |DDS_VHDL|REG10B:u2|DOUT[0] ; |DDS_VHDL|REG10B:u2|DOUT[0]~71 ; cout0 ;
; |DDS_VHDL|REG10B:u2|DOUT[0] ; |DDS_VHDL|REG10B:u2|DOUT[0]~71COUT1_111 ; cout1 ;
; |DDS_VHDL|REG10B:u2|DOUT[5] ; |DDS_VHDL|REG10B:u2|DOUT[5]~91 ; cout0 ;
; |DDS_VHDL|REG10B:u2|DOUT[6] ; |DDS_VHDL|REG10B:u2|DOUT[6]~95 ; cout0 ;
; |DDS_VHDL|REG10B:u2|DOUT[7] ; |DDS_VHDL|REG10B:u2|DOUT[7]~99 ; cout0 ;
; |DDS_VHDL|REG10B:u2|DOUT[7] ; |DDS_VHDL|REG10B:u2|DOUT[7]~99COUT1_117 ; cout1 ;
; |DDS_VHDL|REG10B:u2|DOUT[8] ; |DDS_VHDL|REG10B:u2|DOUT[8] ; regout ;
; |DDS_VHDL|REG10B:u2|DOUT[8] ; |DDS_VHDL|REG10B:u2|DOUT[8]~103 ; cout0 ;
; |DDS_VHDL|REG10B:u2|DOUT[8] ; |DDS_VHDL|REG10B:u2|DOUT[8]~103COUT1_118 ; cout1 ;
; |DDS_VHDL|REG10B:u2|DOUT[9] ; |DDS_VHDL|REG10B:u2|DOUT[9] ; regout ;
; |DDS_VHDL|FWORD[0] ; |DDS_VHDL|FWORD[0] ; combout ;
; |DDS_VHDL|FWORD[1] ; |DDS_VHDL|FWORD[1] ; combout ;
; |DDS_VHDL|FWORD[2] ; |DDS_VHDL|FWORD[2] ; combout ;
; |DDS_VHDL|FWORD[3] ; |DDS_VHDL|FWORD[3] ; combout ;
; |DDS_VHDL|FWORD[4] ; |DDS_VHDL|FWORD[4] ; combout ;
; |DDS_VHDL|FWORD[5] ; |DDS_VHDL|FWORD[5] ; combout ;
; |DDS_VHDL|FWORD[6] ; |DDS_VHDL|FWORD[6] ; combout ;
; |DDS_VHDL|FWORD[7] ; |DDS_VHDL|FWORD[7] ; combout ;
; |DDS_VHDL|FWORD[8] ; |DDS_VHDL|FWORD[8] ; combout ;
; |DDS_VHDL|FWORD[9] ; |DDS_VHDL|FWORD[9] ; combout ;
+-----------------------------+------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+-----------------------------+------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------------------------+------------------------------------------+------------------+
; |DDS_VHDL|REG10B:u3|DOUT[0] ; |DDS_VHDL|REG10B:u3|DOUT[0] ; regout ;
; |DDS_VHDL|REG10B:u3|DOUT[7] ; |DDS_VHDL|REG10B:u3|DOUT[7] ; regout ;
; |DDS_VHDL|REG10B:u3|DOUT[8] ; |DDS_VHDL|REG10B:u3|DOUT[8] ; regout ;
; |DDS_VHDL|REG10B:u3|DOUT[9] ; |DDS_VHDL|REG10B:u3|DOUT[9] ; regout ;
; |DDS_VHDL|REG10B:u2|DOUT[0] ; |DDS_VHDL|REG10B:u2|DOUT[0] ; regout ;
; |DDS_VHDL|REG10B:u2|DOUT[0] ; |DDS_VHDL|REG10B:u2|DOUT[0]~71 ; cout0 ;
; |DDS_VHDL|REG10B:u2|DOUT[0] ; |DDS_VHDL|REG10B:u2|DOUT[0]~71COUT1_111 ; cout1 ;
; |DDS_VHDL|REG10B:u2|DOUT[5] ; |DDS_VHDL|REG10B:u2|DOUT[5]~91 ; cout0 ;
; |DDS_VHDL|REG10B:u2|DOUT[6] ; |DDS_VHDL|REG10B:u2|DOUT[6]~95 ; cout0 ;
; |DDS_VHDL|REG10B:u2|DOUT[7] ; |DDS_VHDL|REG10B:u2|DOUT[7] ; regout ;
; |DDS_VHDL|REG10B:u2|DOUT[7] ; |DDS_VHDL|REG10B:u2|DOUT[7]~99 ; cout0 ;
; |DDS_VHDL|REG10B:u2|DOUT[7] ; |DDS_VHDL|REG10B:u2|DOUT[7]~99COUT1_117 ; cout1 ;
; |DDS_VHDL|REG10B:u2|DOUT[8] ; |DDS_VHDL|REG10B:u2|DOUT[8] ; regout ;
; |DDS_VHDL|REG10B:u2|DOUT[8] ; |DDS_VHDL|REG10B:u2|DOUT[8]~103 ; cout0 ;
; |DDS_VHDL|REG10B:u2|DOUT[8] ; |DDS_VHDL|REG10B:u2|DOUT[8]~103COUT1_118 ; cout1 ;
; |DDS_VHDL|REG10B:u2|DOUT[9] ; |DDS_VHDL|REG10B:u2|DOUT[9] ; regout ;
; |DDS_VHDL|FWORD[0] ; |DDS_VHDL|FWORD[0] ; combout ;
; |DDS_VHDL|FWORD[1] ; |DDS_VHDL|FWORD[1] ; combout ;
; |DDS_VHDL|FWORD[2] ; |DDS_VHDL|FWORD[2] ; combout ;
; |DDS_VHDL|FWORD[3] ; |DDS_VHDL|FWORD[3] ; combout ;
; |DDS_VHDL|FWORD[4] ; |DDS_VHDL|FWORD[4] ; combout ;
; |DDS_VHDL|FWORD[5] ; |DDS_VHDL|FWORD[5] ; combout ;
; |DDS_VHDL|FWORD[6] ; |DDS_VHDL|FWORD[6] ; combout ;
; |DDS_VHDL|FWORD[7] ; |DDS_VHDL|FWORD[7] ; combout ;
; |DDS_VHDL|FWORD[8] ; |DDS_VHDL|FWORD[8] ; combout ;
; |DDS_VHDL|FWORD[9] ; |DDS_VHDL|FWORD[9] ; combout ;
+-----------------------------+------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Mon May 28 16:00:06 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off DDS -c DDS
Warning: Ignored node in vector source file. Can't find corresponding node name "lpm_rom0:u6|address[9]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "lpm_rom0:u6|address[8]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "lpm_rom0:u6|address[7]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "lpm_rom0:u6|address[6]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "lpm_rom0:u6|address[5]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "lpm_rom0:u6|address[4]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "lpm_rom0:u6|address[3]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "lpm_rom0:u6|address[2]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "lpm_rom0:u6|address[1]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "lpm_rom0:u6|address[0]" in design.
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 61.76 %
Info: Number of transitions in simulation is 1588
Info: Quartus II Simulator was successful. 0 errors, 10 warnings
Info: Processing ended: Mon May 28 16:00:06 2007
Info: Elapsed time: 00:00:01
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