dds.fit.eqn

经过仿真验证的

-- Copyright (C) 1991-2005 Altera Corporation
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--F1_q_a[0] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[0] at M4K_X15_Y20
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[0]_PORT_A_address_reg = DFFE(F1_q_a[0]_PORT_A_address, F1_q_a[0]_clock_0, , , );
F1_q_a[0]_clock_0 = GLOBAL(CLK);
F1_q_a[0]_PORT_A_data_out = MEMORY(, , F1_q_a[0]_PORT_A_address_reg, , , , , , F1_q_a[0]_clock_0, , , , , );
F1_q_a[0]_PORT_A_data_out_reg = DFFE(F1_q_a[0]_PORT_A_data_out, F1_q_a[0]_clock_0, , , );
F1_q_a[0] = F1_q_a[0]_PORT_A_data_out_reg[0];

--F1_q_a[9] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[9] at M4K_X15_Y20
F1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[0]_PORT_A_address_reg = DFFE(F1_q_a[0]_PORT_A_address, F1_q_a[0]_clock_0, , , );
F1_q_a[0]_clock_0 = GLOBAL(CLK);
F1_q_a[0]_PORT_A_data_out = MEMORY(, , F1_q_a[0]_PORT_A_address_reg, , , , , , F1_q_a[0]_clock_0, , , , , );
F1_q_a[0]_PORT_A_data_out_reg = DFFE(F1_q_a[0]_PORT_A_data_out, F1_q_a[0]_clock_0, , , );
F1_q_a[9] = F1_q_a[0]_PORT_A_data_out_reg[3];

--F1_q_a[7] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[7] at M4K_X15_Y20
F1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[0]_PORT_A_address_reg = DFFE(F1_q_a[0]_PORT_A_address, F1_q_a[0]_clock_0, , , );
F1_q_a[0]_clock_0 = GLOBAL(CLK);
F1_q_a[0]_PORT_A_data_out = MEMORY(, , F1_q_a[0]_PORT_A_address_reg, , , , , , F1_q_a[0]_clock_0, , , , , );
F1_q_a[0]_PORT_A_data_out_reg = DFFE(F1_q_a[0]_PORT_A_data_out, F1_q_a[0]_clock_0, , , );
F1_q_a[7] = F1_q_a[0]_PORT_A_data_out_reg[2];

--F1_q_a[5] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[5] at M4K_X15_Y20
F1_q_a[0]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[0]_PORT_A_address_reg = DFFE(F1_q_a[0]_PORT_A_address, F1_q_a[0]_clock_0, , , );
F1_q_a[0]_clock_0 = GLOBAL(CLK);
F1_q_a[0]_PORT_A_data_out = MEMORY(, , F1_q_a[0]_PORT_A_address_reg, , , , , , F1_q_a[0]_clock_0, , , , , );
F1_q_a[0]_PORT_A_data_out_reg = DFFE(F1_q_a[0]_PORT_A_data_out, F1_q_a[0]_clock_0, , , );
F1_q_a[5] = F1_q_a[0]_PORT_A_data_out_reg[1];


--F1_q_a[1] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[1] at M4K_X15_Y21
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[1]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[1]_PORT_A_address_reg = DFFE(F1_q_a[1]_PORT_A_address, F1_q_a[1]_clock_0, , , );
F1_q_a[1]_clock_0 = GLOBAL(CLK);
F1_q_a[1]_PORT_A_data_out = MEMORY(, , F1_q_a[1]_PORT_A_address_reg, , , , , , F1_q_a[1]_clock_0, , , , , );
F1_q_a[1]_PORT_A_data_out_reg = DFFE(F1_q_a[1]_PORT_A_data_out, F1_q_a[1]_clock_0, , , );
F1_q_a[1] = F1_q_a[1]_PORT_A_data_out_reg[0];

--F1_q_a[8] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[8] at M4K_X15_Y21
F1_q_a[1]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[1]_PORT_A_address_reg = DFFE(F1_q_a[1]_PORT_A_address, F1_q_a[1]_clock_0, , , );
F1_q_a[1]_clock_0 = GLOBAL(CLK);
F1_q_a[1]_PORT_A_data_out = MEMORY(, , F1_q_a[1]_PORT_A_address_reg, , , , , , F1_q_a[1]_clock_0, , , , , );
F1_q_a[1]_PORT_A_data_out_reg = DFFE(F1_q_a[1]_PORT_A_data_out, F1_q_a[1]_clock_0, , , );
F1_q_a[8] = F1_q_a[1]_PORT_A_data_out_reg[3];

--F1_q_a[4] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[4] at M4K_X15_Y21
F1_q_a[1]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[1]_PORT_A_address_reg = DFFE(F1_q_a[1]_PORT_A_address, F1_q_a[1]_clock_0, , , );
F1_q_a[1]_clock_0 = GLOBAL(CLK);
F1_q_a[1]_PORT_A_data_out = MEMORY(, , F1_q_a[1]_PORT_A_address_reg, , , , , , F1_q_a[1]_clock_0, , , , , );
F1_q_a[1]_PORT_A_data_out_reg = DFFE(F1_q_a[1]_PORT_A_data_out, F1_q_a[1]_clock_0, , , );
F1_q_a[4] = F1_q_a[1]_PORT_A_data_out_reg[2];

--F1_q_a[2] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[2] at M4K_X15_Y21
F1_q_a[1]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[1]_PORT_A_address_reg = DFFE(F1_q_a[1]_PORT_A_address, F1_q_a[1]_clock_0, , , );
F1_q_a[1]_clock_0 = GLOBAL(CLK);
F1_q_a[1]_PORT_A_data_out = MEMORY(, , F1_q_a[1]_PORT_A_address_reg, , , , , , F1_q_a[1]_clock_0, , , , , );
F1_q_a[1]_PORT_A_data_out_reg = DFFE(F1_q_a[1]_PORT_A_data_out, F1_q_a[1]_clock_0, , , );
F1_q_a[2] = F1_q_a[1]_PORT_A_data_out_reg[1];


--F1_q_a[3] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[3] at M4K_X15_Y22
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 2
--Port A Logical Depth: 1024, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
F1_q_a[3]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[3]_PORT_A_address_reg = DFFE(F1_q_a[3]_PORT_A_address, F1_q_a[3]_clock_0, , , );
F1_q_a[3]_clock_0 = GLOBAL(CLK);
F1_q_a[3]_PORT_A_data_out = MEMORY(, , F1_q_a[3]_PORT_A_address_reg, , , , , , F1_q_a[3]_clock_0, , , , , );
F1_q_a[3]_PORT_A_data_out_reg = DFFE(F1_q_a[3]_PORT_A_data_out, F1_q_a[3]_clock_0, , , );
F1_q_a[3] = F1_q_a[3]_PORT_A_data_out_reg[0];

--F1_q_a[6] is lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_l5s:auto_generated|q_a[6] at M4K_X15_Y22
F1_q_a[3]_PORT_A_address = BUS(C2_DOUT[0], C2_DOUT[1], C2_DOUT[2], C2_DOUT[3], C2_DOUT[4], C2_DOUT[5], C2_DOUT[6], C2_DOUT[7], C2_DOUT[8], C2_DOUT[9]);
F1_q_a[3]_PORT_A_address_reg = DFFE(F1_q_a[3]_PORT_A_address, F1_q_a[3]_clock_0, , , );
F1_q_a[3]_clock_0 = GLOBAL(CLK);
F1_q_a[3]_PORT_A_data_out = MEMORY(, , F1_q_a[3]_PORT_A_address_reg, , , , , , F1_q_a[3]_clock_0, , , , , );
F1_q_a[3]_PORT_A_data_out_reg = DFFE(F1_q_a[3]_PORT_A_data_out, F1_q_a[3]_clock_0, , , );
F1_q_a[6] = F1_q_a[3]_PORT_A_data_out_reg[1];


--C2_DOUT[0] is REG10B:u3|DOUT[0] at LC_X14_Y19_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[0]_lut_out = GND;
C2_DOUT[0] = DFFEAS(C2_DOUT[0]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[0], , , VCC);


--C2_DOUT[1] is REG10B:u3|DOUT[1] at LC_X17_Y21_N2
--operation mode is normal

C2_DOUT[1]_lut_out = C1_DOUT[1];
C2_DOUT[1] = DFFEAS(C2_DOUT[1]_lut_out, GLOBAL(CLK), VCC, , , , , , );


--C2_DOUT[2] is REG10B:u3|DOUT[2] at LC_X18_Y20_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[2]_lut_out = GND;
C2_DOUT[2] = DFFEAS(C2_DOUT[2]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[2], , , VCC);


--C2_DOUT[3] is REG10B:u3|DOUT[3] at LC_X14_Y21_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[3]_lut_out = GND;
C2_DOUT[3] = DFFEAS(C2_DOUT[3]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[3], , , VCC);


--C2_DOUT[4] is REG10B:u3|DOUT[4] at LC_X14_Y23_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[4]_lut_out = GND;
C2_DOUT[4] = DFFEAS(C2_DOUT[4]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[4], , , VCC);


--C2_DOUT[5] is REG10B:u3|DOUT[5] at LC_X17_Y20_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[5]_lut_out = GND;
C2_DOUT[5] = DFFEAS(C2_DOUT[5]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[5], , , VCC);


--C2_DOUT[6] is REG10B:u3|DOUT[6] at LC_X19_Y21_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[6]_lut_out = GND;
C2_DOUT[6] = DFFEAS(C2_DOUT[6]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[6], , , VCC);


--C2_DOUT[7] is REG10B:u3|DOUT[7] at LC_X14_Y20_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[7]_lut_out = GND;
C2_DOUT[7] = DFFEAS(C2_DOUT[7]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[7], , , VCC);


--C2_DOUT[8] is REG10B:u3|DOUT[8] at LC_X18_Y21_N2
--operation mode is normal

C2_DOUT[8]_lut_out = C1_DOUT[8];
C2_DOUT[8] = DFFEAS(C2_DOUT[8]_lut_out, GLOBAL(CLK), VCC, , , , , , );


--C2_DOUT[9] is REG10B:u3|DOUT[9] at LC_X14_Y22_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

C2_DOUT[9]_lut_out = GND;
C2_DOUT[9] = DFFEAS(C2_DOUT[9]_lut_out, GLOBAL(CLK), VCC, , , C1_DOUT[9], , , VCC);


--C1_DOUT[0] is REG10B:u2|DOUT[0] at LC_X18_Y22_N0
--operation mode is arithmetic

C1_DOUT[0]_lut_out = FWORD[0] $ C1_DOUT[0];
C1_DOUT[0] = DFFEAS(C1_DOUT[0]_lut_out, GLOBAL(CLK), VCC, , , , , , );

--C1L3 is REG10B:u2|DOUT[0]~71 at LC_X18_Y22_N0
--operation mode is arithmetic

C1L3_cout_0 = FWORD[0] & C1_DOUT[0];
C1L3 = CARRY(C1L3_cout_0);

--C1L4 is REG10B:u2|DOUT[0]~71COUT1_111 at LC_X18_Y22_N0
--operation mode is arithmetic

C1L4_cout_1 = FWORD[0] & C1_DOUT[0];
C1L4 = CARRY(C1L4_cout_1);


--C1_DOUT[1] is REG10B:u2|DOUT[1] at LC_X18_Y22_N1
--operation mode is arithmetic

C1_DOUT[1]_lut_out = FWORD[1] $ C1_DOUT[1] $ C1L3;
C1_DOUT[1] = DFFEAS(C1_DOUT[1]_lut_out, GLOBAL(CLK), VCC, , , , , , );

--C1L6 is REG10B:u2|DOUT[1]~75 at LC_X18_Y22_N1
--operation mode is arithmetic

C1L6_cout_0 = FWORD[1] & !C1_DOUT[1] & !C1L3 # !FWORD[1] & (!C1L3 # !C1_DOUT[1]);
C1L6 = CARRY(C1L6_cout_0);

--C1L7 is REG10B:u2|DOUT[1]~75COUT1_112 at LC_X18_Y22_N1
--operation mode is arithmetic

C1L7_cout_1 = FWORD[1] & !C1_DOUT[1] & !C1L4 # !FWORD[1] & (!C1L4 # !C1_DOUT[1]);
C1L7 = CARRY(C1L7_cout_1);


--C1_DOUT[2] is REG10B:u2|DOUT[2] at LC_X18_Y22_N2
--operation mode is arithmetic

C1_DOUT[2]_lut_out = C1_DOUT[2] $ FWORD[2] $ !C1L6;
C1_DOUT[2] = DFFEAS(C1_DOUT[2]_lut_out, GLOBAL(CLK), VCC, , , , , , );

--C1L9 is REG10B:u2|DOUT[2]~79 at LC_X18_Y22_N2
--operation mode is arithmetic

C1L9_cout_0 = C1_DOUT[2] & (FWORD[2] # !C1L6) # !C1_DOUT[2] & FWORD[2] & !C1L6;
C1L9 = CARRY(C1L9_cout_0);

--C1L10 is REG10B:u2|DOUT[2]~79COUT1_113 at LC_X18_Y22_N2
--operation mode is arithmetic

C1L10_cout_1 = C1_DOUT[2] & (FWORD[2] # !C1L7) # !C1_DOUT[2] & FWORD[2] & !C1L7;
C1L10 = CARRY(C1L10_cout_1);


--C1_DOUT[3] is REG10B:u2|DOUT[3] at LC_X18_Y22_N3
--operation mode is arithmetic