com_sync.m

数字通信第四版原书的例程

		'position',[370,205,390,225])

add_block('built-in/Outport',[sys,'/',['Charge pump',13,'PLL/out_2']])
set_param([sys,'/',['Charge pump',13,'PLL/out_2']],...
		'Port','2',...
		'position',[320,25,340,45])
add_line([sys,'/',['Charge pump',13,'PLL']],[295,80;350,80])
add_line([sys,'/',['Charge pump',13,'PLL']],[310,80;310,155;225,155])
add_line([sys,'/',['Charge pump',13,'PLL']],[200,80;235,80])
add_line([sys,'/',['Charge pump',13,'PLL']],[385,80;410,80])
add_line([sys,'/',['Charge pump',13,'PLL']],[160,155;110,155;110,90;130,90])
add_line([sys,'/',['Charge pump',13,'PLL']],[65,70;130,70])
add_line([sys,'/',['Charge pump',13,'PLL']],[110,155;110,215;365,215])
add_line([sys,'/',['Charge pump',13,'PLL']],[210,80;210,35;315,35])
set_param([sys,'/',['Charge pump',13,'PLL']],...
		'Mask Display','Charge\npump\nPLL',...
		'Mask Type','Charge pump PLL')
set_param([sys,'/',['Charge pump',13,'PLL']],...
		'Mask Dialogue','Output the phase shifting signal at 1st\nport; the detected phase error at 2nd\nport; VOC output at 3rd port.|Lowpass filter numerator:|Lowpass filter Denominator:|Oscillation frequency (Hz):|Oscillation Phase (rad):|Oscillation Amplitude:|Gain at the output:')
set_param([sys,'/',['Charge pump',13,'PLL']],...
		'Mask Translate','Fn=@1;Fd=@2;Fc=@3;Ph=@4;Ac=@5;G=@6;Cu=1;')
set_param([sys,'/',['Charge pump',13,'PLL']],...
		'Mask Help','This block uses a digital charge pump to detect the phase shifting from the oscillation signal. The first output is the detected phase shift. The second output is the detected phase error output from phase detector. The third output is the matching signal for the input. Note a 180 degree phase difference between the input signal and the matching signal.')
set_param([sys,'/',['Charge pump',13,'PLL']],...
		'Mask Entries','[3.0002,  0, 40002]\/[1, 67.46, 2270.9, 40002]\/100/2/pi\/pi\/1\/3\/')


%     Finished composite block ['Charge pump',13,'PLL'].

set_param([sys,'/',['Charge pump',13,'PLL']],...
		'position',[30,128,110,172])


%     Subsystem  ['Linearized baseband',13,'model for PLL'].

new_system([sys,'/',['Linearized baseband',13,'model for PLL']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL']],'Location',[94,80,709,266])

add_block('built-in/Gain',[sys,'/',['Linearized baseband',13,'model for PLL/Gain1']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Gain1']],...
		'Gain','pi2',...
		'position',[140,18,175,52])

add_block('built-in/Gain',[sys,'/',['Linearized baseband',13,'model for PLL/Gain']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Gain']],...
		'orientation',2,...
		'Gain','pi2',...
		'position',[255,95,290,125])

add_block('built-in/Gain',[sys,'/',['Linearized baseband',13,'model for PLL/Gain2']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Gain2']],...
		'Gain','Kc',...
		'position',[325,25,370,55])

add_block('built-in/Sum',[sys,'/',['Linearized baseband',13,'model for PLL/Sum']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Sum']],...
		'inputs','+-',...
		'position',[220,30,240,50])


%     Subsystem  ['Linearized baseband',13,'model for PLL/Module',13,'integrator'].

new_system([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],'Location',[196,490,621,627])

add_block('built-in/Inport',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/in_1']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/in_1']],...
		'position',[35,15,55,35])

add_block('built-in/Memory',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/Memory']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/Memory']],...
		'orientation',2,...
		'x0','init',...
		'position',[210,75,260,105])

add_block('built-in/Fcn',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/module']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/module']],...
		'Expr','rem(u[1],modu)',...
		'position',[235,29,325,51])

add_block('built-in/Reset Integrator',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/Reset',13,'integrator']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/Reset',13,'integrator']],...
		'position',[110,19,150,51])

add_block('built-in/Constant',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/one']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/one']],...
		'orientation',3,...
		'move name',0,...
		'position',[70,55,90,75])

add_block('built-in/Sum',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/Sum']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/Sum']],...
		'position',[195,30,215,50])

add_block('built-in/Outport',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/out_1']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator/out_1']],...
		'position',[370,30,390,50])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],[205,90;180,90;190,45])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],[155,35;190,35])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],[220,40;230,40])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],[60,25;105,25])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],[80,50;80,35;105,35])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],[330,40;365,40])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],[340,40;340,90;265,90])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],...
		'Mask Display','Mod\nint',...
		'Mask Type','Module Integrator')
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],...
		'Mask Dialogue','Module the given number when state exceed limit|Module bound:|Initial value:',...
		'Mask Translate','init=@2; modu=@1;')
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],...
		'Mask Help','The absolute value of this integrator will not exceed the specified module bound. The state value is set to be zero when the module bound is reached. This block can only be used for scale value calculation.')
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],...
		'Mask Entries','1\/0\/')


%     Finished composite block ['Linearized baseband',13,'model for PLL/Module',13,'integrator'].

set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator']],...
		'position',[65,17,115,53])

add_block('built-in/Outport',[sys,'/',['Linearized baseband',13,'model for PLL/Estimated',13,'phase']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Estimated',13,'phase']],...
		'position',[580,30,600,50])


%     Subsystem  ['Linearized baseband',13,'model for PLL/Module',13,'integrator1'].

new_system([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],'Location',[196,490,621,627])

add_block('built-in/Outport',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/out_1']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/out_1']],...
		'position',[370,30,390,50])

add_block('built-in/Sum',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/Sum']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/Sum']],...
		'position',[195,30,215,50])

add_block('built-in/Constant',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/one']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/one']],...
		'orientation',3,...
		'move name',0,...
		'position',[70,55,90,75])

add_block('built-in/Reset Integrator',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/Reset',13,'integrator']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/Reset',13,'integrator']],...
		'position',[110,19,150,51])

add_block('built-in/Fcn',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/module']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/module']],...
		'Expr','rem(u[1],modu)',...
		'position',[235,29,325,51])

add_block('built-in/Memory',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/Memory']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/Memory']],...
		'orientation',2,...
		'x0','init',...
		'position',[210,75,260,105])

add_block('built-in/Inport',[sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/in_1']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1/in_1']],...
		'position',[35,15,55,35])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],[330,40;365,40])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],[340,40;340,90;265,90])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],[80,50;80,35;105,35])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],[60,25;105,25])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],[220,40;230,40])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],[155,35;190,35])
add_line([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],[205,90;180,90;190,45])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],...
		'Mask Display','Mod\nint',...
		'Mask Type','Module Integrator')
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],...
		'Mask Dialogue','Module the given number when state exceed limit|Module bound:|Initial value:',...
		'Mask Translate','init=@2; modu=@1;')
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],...
		'Mask Help','The absolute value of this integrator will not exceed the specified module bound. The state value is set to be zero when the module bound is reached. This block can only be used for scale value calculation.')
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],...
		'Mask Entries','1\/0\/')


%     Finished composite block ['Linearized baseband',13,'model for PLL/Module',13,'integrator1'].

set_param([sys,'/',['Linearized baseband',13,'model for PLL/Module',13,'integrator1']],...
		'orientation',2,...
		'position',[330,90,380,130])

add_block('built-in/Inport',[sys,'/',['Linearized baseband',13,'model for PLL/in_1']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/in_1']],...
		'position',[15,25,35,45])

add_block('built-in/Transfer Fcn',[sys,'/',['Linearized baseband',13,'model for PLL/Filter']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Filter']],...
		'Numerator','Fn',...
		'Denominator','Fd',...
		'position',[420,21,470,59])

add_block('built-in/Gain',[sys,'/',['Linearized baseband',13,'model for PLL/Gain3']])
set_param([sys,'/',['Linearized baseband',13,'model for PLL/Gain3']],...
		'Gain','G',...
		'position',[520,27,545,53])
add_line([sys,'/',['Linearized baseband',13,'model for PLL']],[40,35;60,35])
add_line([sys,'/',['Linearized baseband',13,'model for PLL']],[475,40;505,40;505,110;385,110])
add_line([sys,'/',['Linearized baseband',13,'model for PLL']],[250,110;190,110;190,45;215,45])
add_line([sys,'/',['Linearized baseband',13,'model for PLL']],[180,35;215,35])
add_line([sys,'/',['Linearized baseband',13,'model for PLL']],[375,40;415,40])
add_line([sys,'/',['Linearized baseband',13,'model for PLL']],[550,40;575,40])
add_line([sys,'/',['Linearized baseband',13,'model for PLL']],[120,35;135,35])
add_line([sys,'/',['Linearized baseband',13,'model for PLL']],[325,110;295,110])
add_line([sys,'/',['Linearized baseband',13,'model for PLL']],[505,40;515,40])
add_line([sys,'/',['Linearized baseband',13,'model for PLL']],[245,40;320,40])
set_param([sys,'/',['Linearized baseband',13,'model for PLL']],...
		'Mask Display','Linearized\nbaseband\nPLL',...
		'Mask Type','Linearized baseband PLL model')
set_param([sys,'/',['Linearized baseband',13,'model for PLL']],...
		'Mask Dialogue','Output the phase shifting of the input\nsignal from the oscillation frequency.|Lowpass filter numerator:|Lowpass filter denominator:|Oscillation frequency (Hz):|Oscillation amplitude:|Gain at the output:')
set_param([sys,'/',['Linearized baseband',13,'model for PLL']],...
		'Mask Translate','Fn=@1;Fd=@2;Fc=@3;pi2=2*pi;Kc=@4/2;G=@5;')
set_param([sys,'/',['Linearized baseband',13,'model for PLL']],...
		'Mask Help','This block detects the phase shifting of the input signal. The input to this block is an oscillation signal with possible phase shifting. The block detects the phase shifting value using PLL technique. Design the lowpass filter to pass the phase changing signal and to eliminate the oscillation signal.')
set_param([sys,'/',['Linearized baseband',13,'model for PLL']],...
		'Mask Entries','[3.0002,  0, 40002]\/[1, 67.46, 2270.9, 40002]\/100/2/pi\/1\/2\/')


%     Finished composite block ['Linearized baseband',13,'model for PLL'].

set_param([sys,'/',['Linearized baseband',13,'model for PLL']],...
		'position',[155,128,235,172])

add_block('built-in/Note',[sys,'/','Synchronization Library'])
set_param([sys,'/','Synchronization Library'],...
		'ForeGround',3,...
		'Font Weight','bold',...
		'Font Size',12,...
		'position',[185,6,190,11])

drawnow

% Return any arguments.
if (nargin | nargout)
	% Must use feval here to access system in memory
	if (nargin > 3)
		if (flag == 0)
			eval(['[ret,x0,str,ts,xts]=',sys,'(t,x,u,flag);'])
		else
			eval(['ret =', sys,'(t,x,u,flag);'])
		end
	else
		[ret,x0,str,ts,xts] = feval(sys);
	end
else
	drawnow % Flash up the model and execute load callback
end