extrflip.m

数字通信第四版原书的例程

set_param([sys,'/','JK flip-flop'],...
		'position',[165,112,210,188])


%     Subsystem  'SR flip-flop'.

new_system([sys,'/','SR flip-flop'])
set_param([sys,'/','SR flip-flop'],'Location',[136,202,614,399])

add_block('built-in/Transport Delay',[sys,'/','SR flip-flop/Transport Delay1'])
set_param([sys,'/','SR flip-flop/Transport Delay1'],...
		'Initial Input','1',...
		'position',[100,10,150,40])


%     Subsystem  'SR flip-flop/AND'.

new_system([sys,'/','SR flip-flop/AND'])
set_param([sys,'/','SR flip-flop/AND'],'Location',[59,237,323,377])

add_block('built-in/Outport',[sys,'/','SR flip-flop/AND/out_1'])
set_param([sys,'/','SR flip-flop/AND/out_1'],...
		'position',[215,65,235,85])

add_block('built-in/Combinatorial Logic',[sys,'/','SR flip-flop/AND/AND'])
set_param([sys,'/','SR flip-flop/AND/AND'],...
		'Truth Table','[0;0;0;1]',...
		'position',[130,55,185,95])

add_block('built-in/Mux',[sys,'/','SR flip-flop/AND/Mux'])
set_param([sys,'/','SR flip-flop/AND/Mux'],...
		'inputs','2',...
		'position',[65,55,95,90])

add_block('built-in/Inport',[sys,'/','SR flip-flop/AND/in_1'])
set_param([sys,'/','SR flip-flop/AND/in_1'],...
		'position',[15,55,35,75])

add_block('built-in/Inport',[sys,'/','SR flip-flop/AND/in_2'])
set_param([sys,'/','SR flip-flop/AND/in_2'],...
		'Port','2',...
		'position',[15,70,35,90])
add_line([sys,'/','SR flip-flop/AND'],[100,75;125,75])
add_line([sys,'/','SR flip-flop/AND'],[40,65;60,65])
add_line([sys,'/','SR flip-flop/AND'],[40,80;60,80])
add_line([sys,'/','SR flip-flop/AND'],[190,75;210,75])
set_param([sys,'/','SR flip-flop/AND'],...
		'Mask Display','AND',...
		'Mask Type','AND',...
		'Mask Dialogue','AND Gate',...
		'Mask Help','Calculates the logical AND of the two inputs.')


%     Finished composite block 'SR flip-flop/AND'.

set_param([sys,'/','SR flip-flop/AND'],...
		'position',[235,19,270,46])

add_block('built-in/Inport',[sys,'/','SR flip-flop/in_1'])
set_param([sys,'/','SR flip-flop/in_1'],...
		'Port','2',...
		'position',[45,40,65,60])

add_block('built-in/Fcn',[sys,'/','SR flip-flop/Fcn1'])
set_param([sys,'/','SR flip-flop/Fcn1'],...
		'Expr','u[1]<.2',...
		'position',[170,13,200,37])

add_block('built-in/Fcn',[sys,'/','SR flip-flop/Fcn'])
set_param([sys,'/','SR flip-flop/Fcn'],...
		'orientation',2,...
		'Expr','u[1]>.2',...
		'position',[190,148,225,172])

add_block('built-in/Transport Delay',[sys,'/','SR flip-flop/Transport Delay'])
set_param([sys,'/','SR flip-flop/Transport Delay'],...
		'orientation',2,...
		'Initial Input','ini',...
		'position',[270,145,315,175])

add_block('built-in/Combinatorial Logic',[sys,'/','SR flip-flop/Logic'])
set_param([sys,'/','SR flip-flop/Logic'],...
		'Truth Table','[0 1;1 0;0 1;1 0;0 1;1 0;0 1;1 0;0 1;1 0;0 1;0 1;1 0;1 0;0 0;0 0]',...
		'position',[220,80,275,120])

add_block('built-in/Mux',[sys,'/','SR flip-flop/Mux'])
set_param([sys,'/','SR flip-flop/Mux'],...
		'position',[170,77,200,123])

add_block('built-in/Demux',[sys,'/','SR flip-flop/Demux'])
set_param([sys,'/','SR flip-flop/Demux'],...
		'outputs','2',...
		'position',[300,80,340,115])

add_block('built-in/Outport',[sys,'/','SR flip-flop/out_1'])
set_param([sys,'/','SR flip-flop/out_1'],...
		'position',[385,80,405,100])

add_block('built-in/Inport',[sys,'/','SR flip-flop/in_3'])
set_param([sys,'/','SR flip-flop/in_3'],...
		'Port','3',...
		'position',[120,95,140,115])

add_block('built-in/Inport',[sys,'/','SR flip-flop/in_2'])
set_param([sys,'/','SR flip-flop/in_2'],...
		'position',[85,85,105,105])

add_block('built-in/Outport',[sys,'/','SR flip-flop/out_2'])
set_param([sys,'/','SR flip-flop/out_2'],...
		'Port','2',...
		'position',[410,95,430,115])
add_line([sys,'/','SR flip-flop'],[145,105;165,105])
add_line([sys,'/','SR flip-flop'],[110,95;165,95])
add_line([sys,'/','SR flip-flop'],[205,100;215,100])
add_line([sys,'/','SR flip-flop'],[280,100;295,100])
add_line([sys,'/','SR flip-flop'],[345,105;405,105])
add_line([sys,'/','SR flip-flop'],[345,90;360,90;360,160;320,160])
add_line([sys,'/','SR flip-flop'],[360,90;380,90])
add_line([sys,'/','SR flip-flop'],[155,25;165,25])
add_line([sys,'/','SR flip-flop'],[205,25;230,25])
add_line([sys,'/','SR flip-flop'],[275,35;290,35;290,60;160,60;165,85])
add_line([sys,'/','SR flip-flop'],[70,50;215,50;215,40;230,40])
add_line([sys,'/','SR flip-flop'],[70,50;80,50;80,25;95,25])
add_line([sys,'/','SR flip-flop'],[265,160;230,160])
add_line([sys,'/','SR flip-flop'],[185,160;160,160;165,115])
set_param([sys,'/','SR flip-flop'],...
		'Mask Display','S    1\n\n>        \n\nR    0',...
		'Mask Type','SR flip-flop',...
		'Mask Dialogue','SR flip-flop|Initial State for Output "1":',...
		'Mask Translate','ini=(@1~=0);')
set_param([sys,'/','SR flip-flop'],...
		'Mask Help','When the clock signal is high, if S is one, the uncomplemented output will change to one.  If R is one, the uncomplemented output will become zero.  If both S and R are one, the output will be in an undefined state.')
set_param([sys,'/','SR flip-flop'],...
		'Mask Entries','0\/')


%     Finished composite block 'SR flip-flop'.

set_param([sys,'/','SR flip-flop'],...
		'position',[45,112,90,188])


%     Subsystem  'Latch'.

new_system([sys,'/','Latch'])
set_param([sys,'/','Latch'],'Location',[102,336,551,502])

add_block('built-in/Inport',[sys,'/','Latch/in_2'])
set_param([sys,'/','Latch/in_2'],...
		'Port','2',...
		'position',[50,65,70,85])

add_block('built-in/Inport',[sys,'/','Latch/in_1'])
set_param([sys,'/','Latch/in_1'],...
		'position',[20,50,40,70])

add_block('built-in/Mux',[sys,'/','Latch/Mux'])
set_param([sys,'/','Latch/Mux'],...
		'inputs','3',...
		'position',[135,59,165,91])

add_block('built-in/Outport',[sys,'/','Latch/out_1'])
set_param([sys,'/','Latch/out_1'],...
		'position',[355,55,375,75])

add_block('built-in/Outport',[sys,'/','Latch/out_2'])
set_param([sys,'/','Latch/out_2'],...
		'Port','2',...
		'position',[395,70,415,90])

add_block('built-in/Transport Delay',[sys,'/','Latch/Transport Delay'])
set_param([sys,'/','Latch/Transport Delay'],...
		'orientation',2,...
		'Initial Input','ini',...
		'position',[250,120,295,150])

add_block('built-in/Combinatorial Logic',[sys,'/','Latch/Logic'])
set_param([sys,'/','Latch/Logic'],...
		'Truth Table','[0 1;1 0;0 1;0 1;1 0;1 0;0 0;0 0]',...
		'position',[195,55,250,95])

add_block('built-in/Demux',[sys,'/','Latch/Demux'])
set_param([sys,'/','Latch/Demux'],...
		'outputs','2',...
		'position',[275,55,315,90])

add_block('built-in/Fcn',[sys,'/','Latch/Fcn'])
set_param([sys,'/','Latch/Fcn'],...
		'orientation',2,...
		'Expr','u[1]>.2',...
		'position',[170,123,205,147])
add_line([sys,'/','Latch'],[320,80;390,80])
add_line([sys,'/','Latch'],[255,75;270,75])
add_line([sys,'/','Latch'],[170,75;190,75])
add_line([sys,'/','Latch'],[45,60;105,60;105,65;130,65])
add_line([sys,'/','Latch'],[75,75;130,75])
add_line([sys,'/','Latch'],[245,135;210,135])
add_line([sys,'/','Latch'],[165,135;110,135;110,85;130,85])
add_line([sys,'/','Latch'],[320,65;350,65])
add_line([sys,'/','Latch'],[335,65;335,135;300,135])
set_param([sys,'/','Latch'],...
		'Mask Display','S  1\n\nR  0',...
		'Mask Type','Latch',...
		'Mask Dialogue','Latch|Initial State for Output "1":',...
		'Mask Translate','ini=(@1~=0);')
set_param([sys,'/','Latch'],...
		'Mask Help','Latches the S input.  When S (set) is one, the uncomplemented output (1) becomes one.  The output remains one until the R (reset) input becomes one, forcing the output to zero.  If both R and S are one, the latch will be in an undefined state.')
set_param([sys,'/','Latch'],...
		'Mask Entries','0\/')


%     Finished composite block 'Latch'.

set_param([sys,'/','Latch'],...
		'position',[50,32,85,83])

add_block('built-in/Note',[sys,'/',['NOTE:',13,'The flip-flop blocks are triggered by the',13,'rising edge of a clock signal.  The above ',13,'clock block is specifically designed to   ',13,'provide a sharp rising and falling edge   ',13,'for use with these flip-flops. Other input ',13,'signals may result in error. ']])
set_param([sys,'/',['NOTE:',13,'The flip-flop blocks are triggered by the',13,'rising edge of a clock signal.  The above ',13,'clock block is specifically designed to   ',13,'provide a sharp rising and falling edge   ',13,'for use with these flip-flops. Other input ',13,'signals may result in error. ']],...
		'position',[140,285,145,290])


%     Subsystem  'Clock'.

new_system([sys,'/','Clock'])
set_param([sys,'/','Clock'],'Location',[471,305,788,438])

add_block('built-in/Sum',[sys,'/','Clock/Sum'])
set_param([sys,'/','Clock/Sum'],...
		'inputs','+-',...
		'position',[115,30,135,50])

add_block('built-in/Unit Delay',[sys,'/','Clock/Unit Delay'])
set_param([sys,'/','Clock/Unit Delay'],...
		'orientation',2,...
		'Sample time','duration',...
		'position',[125,80,175,100])

add_block('built-in/Outport',[sys,'/','Clock/out_1'])
set_param([sys,'/','Clock/out_1'],...
		'position',[240,30,260,50])

add_block('built-in/Constant',[sys,'/','Clock/Constant'])
set_param([sys,'/','Clock/Constant'],...
		'position',[25,25,45,45])

add_block('built-in/Discrete Transfer Fcn',[sys,'/','Clock/Dis. Transfer Fcn'])
set_param([sys,'/','Clock/Dis. Transfer Fcn'],...
		'Denominator','[1 ]',...
		'Sample time','[duration, duration/20]',...
		'position',[210,202,255,238])

add_block('built-in/Discrete Transfer Fcn',[sys,'/','Clock/Dis. Transfer Fcn1'])
set_param([sys,'/','Clock/Dis. Transfer Fcn1'],...
		'Denominator','[1 ]',...
		'Sample time','[duration, duration-duration/20]',...
		'position',[90,202,135,238])
add_line([sys,'/','Clock'],[50,35;110,35])
add_line([sys,'/','Clock'],[140,40;210,40;210,90;180,90])
add_line([sys,'/','Clock'],[120,90;85,90;85,45;110,45])
add_line([sys,'/','Clock'],[140,40;235,40])
set_param([sys,'/','Clock'],...
		'Mask Display','plot(0,0,100,100,[90,75,75,60,60,35,35,20,20,10],[20,20,80,80,19,20,80,80,20,20])',...
		'Mask Type','Digital clock')
set_param([sys,'/','Clock'],...
		'Mask Dialogue','Digital clock.\nOutput is set to 1 for the first half of the period.|Period:',...
		'Mask Translate','duration = @1/2;',...
		'Mask Help','Digital clock for logic systems.')
set_param([sys,'/','Clock'],...
		'Mask Entries','2\/')


%     Finished composite block 'Clock'.

set_param([sys,'/','Clock'],...
		'position',[50,231,90,259])


%     Subsystem  'Demo'.

new_system([sys,'/','Demo'])
set_param([sys,'/','Demo'],'Location',[60,206,282,425])
set_param([sys,'/','Demo'],...
		'Mask Display','DEMO',...
		'Mask Dialogue','eval(''logdemo'');')


%     Finished composite block 'Demo'.

set_param([sys,'/','Demo'],...
		'hide name',0,...
		'position',[162,229,209,261])

add_block('built-in/Note',[sys,'/','Flip-flops'])
set_param([sys,'/','Flip-flops'],...
		'position',[125,5,130,10])

drawnow

% Return any arguments.
if (nargin | nargout)
	% Must use feval here to access system in memory
	if (nargin > 3)
		if (flag == 0)
			eval(['[ret,x0,str,ts,xts]=',sys,'(t,x,u,flag);'])
		else
			eval(['ret =', sys,'(t,x,u,flag);'])
		end
	else
		[ret,x0,str,ts,xts] = feval(sys);
	end
else
	drawnow % Flash up the model and execute load callback
end