📄 portisr.lst
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135:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
136:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* The preemptive scheduler is defined as "naked" as the full context is
137:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** saved on entry as part of the context switch. */
138:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vPreemptiveTick( void ) __attribute__((naked));
139:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vPreemptiveTick( void )
140:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** {
141:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Save the context of the interrupted task. */
142:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** portSAVE_CONTEXT();
143:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
144:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Increment the RTOS tick count, then look for the highest priority
145:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** task that is ready to run. */
146:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** vTaskIncrementTick();
147:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** vTaskSwitchContext();
148:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
149:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Ready for the next interrupt. */
150:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** T0IR = portTIMER_MATCH_ISR_BIT;
151:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** VICVectAddr = portCLEAR_VIC_INTERRUPT;
152:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
153:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Restore the context of the new task. */
154:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** portRESTORE_CONTEXT();
155:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** }
156:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
157:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** #endif
158:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /*-----------------------------------------------------------*/
159:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
160:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /*
161:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * The interrupt management utilities can only be called from ARM mode. When
162:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * THUMB_INTERWORK is defined the utilities are defined as functions here to
163:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
164:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * the utilities are defined as macros in portmacro.h - as per other ports.
165:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** */
166:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** #ifdef THUMB_INTERWORK
167:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
168:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
169:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
170:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
171:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vPortDisableInterruptsFromThumb( void )
172:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** {
54 retend = 0, frame = 0
55 @ frame_needed = 0, uses_anonymous_args = 0
56 .loc 1 173 0
57 STMDB SP!, {R0}
58 MRS R0, CPSR
173:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** asm volatile (
59 R0, R0, #0xC0
60 004c 01002DE9 MSR CPSR, R0
61 0050 00000FE1 LDMIA SP!, {R0}
62 0054 C00080E3 BX R14
63 0058 00F029E1 .loc 1 180 0
64 005c 0100BDE8 .LFE5:
174:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "STMDB SP!, {R0} \n\t" /* Push R0. */
175:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "MRS R0, CPSR \n\t" /* Get CPSR. */
176:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
177:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "MSR CPSR, R0 \n\t" /* Write back modified value. */
178:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "LDMIA SP!, {R0} \n\t" /* Pop R0. */
179:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "BX R14" ); /* Return back to thumb. */
180:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** }
66 2
67 .global vPortEnableInterruptsFromThumb
69 vPortEnableInterruptsFromThumb:
70 .LFB6:
71 .loc 1 183 0
72 @ Function supports interworking.
73 @ Naked Function: prologue and epilogue provided by programmer.
181:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
182:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vPortEnableInterruptsFromThumb( void )
183:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** {
74 = 0, pretend = 0, frame = 0
75 @ frame_needed = 0, uses_anonymous_args = 0
76 .loc 1 184 0
77 STMDB SP!, {R0}
78 MRS R0, CPSR
184:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** asm volatile (
79 R0, R0, #0xC0
80 0064 01002DE9 MSR CPSR, R0
81 0068 00000FE1 LDMIA SP!, {R0}
82 006c C000C0E3 BX R14
83 0070 00F029E1 .loc 1 191 0
84 0074 0100BDE8 .LFE6:
185:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "STMDB SP!, {R0} \n\t" /* Push R0. */
186:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "MRS R0, CPSR \n\t" /* Get CPSR. */
187:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
188:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "MSR CPSR, R0 \n\t" /* Write back modified value. */
189:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "LDMIA SP!, {R0} \n\t" /* Pop R0. */
190:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "BX R14" ); /* Return back to thumb. */
191:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** }
86 2
87 .global vPortEnterCritical
89 vPortEnterCritical:
90 .LFB7:
91 .loc 1 200 0
92 @ Function supports interworking.
93 @ args = 0, pretend = 0, frame = 0
192:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
193:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** #endif /* THUMB_INTERWORK */
194:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
195:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* The code generated by the GCC compiler uses the stack in different ways at
196:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** different optimisation levels. The interrupt flags can therefore not always
197:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** be saved to the stack. Instead the critical section nesting level is stored
198:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** in a variable, which is then saved as part of the stack context. */
199:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vPortEnterCritical( void )
200:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** {
94 _needed = 0, uses_anonymous_args = 0
95 @ link register save eliminated.
96 @ lr needed for prologue
97 .loc 1 202 0
98 STMDB SP!, {R0}
99 MRS R0, CPSR
201:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
202:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** asm volatile (
100 0, R0, #0xC0
101 007c 01002DE9 MSR CPSR, R0
102 0080 00000FE1 LDMIA SP!, {R0}
103 0084 C00080E3 .loc 1 212 0
104 0088 00F029E1 ldr r2, .L11
105 008c 0100BDE8 ldr r3, [r2, #0]
203:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "STMDB SP!, {R0} \n\t" /* Push R0. */
204:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "MRS R0, CPSR \n\t" /* Get CPSR. */
205:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
206:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "MSR CPSR, R0 \n\t" /* Write back modified value. */
207:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** "LDMIA SP!, {R0}" ); /* Pop R0. */
208:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
209:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Now interrupts are disabled ulCriticalNesting can be accessed
210:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** directly. Increment ulCriticalNesting to keep a count of how many times
211:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** portENTER_CRITICAL() has been called. */
212:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** ulCriticalNesting++;
106 3, r3, #1
107 0090 0C209FE5 str r3, [r2, #0]
108 0094 003092E5 .loc 1 213 0
109 0098 013083E2 bx lr
110 009c 003082E5 .L12:
213:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** }
111 gn 2
112 00a0 1EFF2FE1 .L11:
113 .word ulCriticalNesting
114 .LFE7:
116 00a4 00000000 .align 2
117 .global vPortExitCritical
119 vPortExitCritical:
120 .LFB8:
121 .loc 1 216 0
122 @ Function supports interworking.
123 @ args = 0, pretend = 0, frame = 0
214:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
215:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vPortExitCritical( void )
216:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** {
124 ed = 0, uses_anonymous_args = 0
125 @ link register save eliminated.
126 .loc 1 217 0
127 ldr r2, .L18
128 ldr r3, [r2, #0]
217:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** if( ulCriticalNesting > portNO_CRITICAL_NESTING )
129 r3, #0
130 00a8 38209FE5 .loc 1 216 0
131 00ac 003092E5 @ lr needed for prologue
132 00b0 000053E3 .loc 1 217 0
133 bxeq lr
134 .loc 1 220 0
135 ldr r3, [r2, #0]
136 00b4 1EFF2F01 sub r3, r3, #1
218:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** {
219:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Decrement the nesting count as we are leaving a critical section. */
220:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** ulCriticalNesting--;
137 [r2, #0]
138 00b8 003092E5 .loc 1 224 0
139 00bc 013043E2 ldr r3, [r2, #0]
140 00c0 003082E5 cmp r3, #0
221:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
222:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* If the nesting level has reached zero then interrupts should be
223:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** re-enabled. */
224:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** if( ulCriticalNesting == portNO_CRITICAL_NESTING )
141 e lr
142 00c4 003092E5 .loc 1 227 0
143 00c8 000053E3 STMDB SP!, {R0}
144 00cc 1EFF2F11 MRS R0, CPSR
225:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** {
226:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Enable interrupts as per portEXIT_CRITICAL(). */
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