📄 portisr.lst
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1 .file "portISR.c"
9 .Ltext0:
10 .align 2
11 .global vPortISRStartFirstTask
13 vPortISRStartFirstTask:
14 .LFB2:
15 .file 1 "rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c"
1:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /*
2:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** FreeRTOS.org V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
3:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
4:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** This file is part of the FreeRTOS.org distribution.
5:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
6:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** FreeRTOS.org is free software; you can redistribute it and/or modify
7:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** it under the terms of the GNU General Public License as published by
8:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** the Free Software Foundation; either version 2 of the License, or
9:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** (at your option) any later version.
10:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
11:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** FreeRTOS.org is distributed in the hope that it will be useful,
12:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** but WITHOUT ANY WARRANTY; without even the implied warranty of
13:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** GNU General Public License for more details.
15:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
16:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** You should have received a copy of the GNU General Public License
17:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** along with FreeRTOS.org; if not, write to the Free Software
18:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
20:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** A special exception to the GPL can be applied should you wish to distribute
21:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** a combined work that includes FreeRTOS.org, without being obliged to provide
22:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** the source code for any proprietary components. See the licensing section
23:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** of http://www.FreeRTOS.org for full details of how and when the exception
24:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** can be applied.
25:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
26:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** ***************************************************************************
27:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** See http://www.FreeRTOS.org for documentation, latest information, license
28:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** and contact details. Please ensure to read the configuration and relevant
29:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** port sections of the online documentation.
30:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** ***************************************************************************
31:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** */
32:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
33:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
34:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /*-----------------------------------------------------------
35:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * Components that can be compiled to either ARM or THUMB mode are
36:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * contained in port.c The ISR routines, which can only be compiled
37:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * to ARM mode, are contained in this file.
38:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** *----------------------------------------------------------*/
39:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
40:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /*
41:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** Changes from V2.5.2
42:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
43:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** + The critical section management functions have been changed. These no
44:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** longer modify the stack and are safe to use at all optimisation levels.
45:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** The functions are now also the same for both ARM and THUMB modes.
46:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
47:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** Changes from V2.6.0
48:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
49:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** + Removed the 'static' from the definition of vNonPreemptiveTick() to
50:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** allow the demo to link when using the cooperative scheduler.
51:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
52:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** Changes from V3.2.4
53:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
54:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** + The assembler statements are now included in a single asm block rather
55:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** than each line having its own asm block.
56:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** */
57:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
58:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
59:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Scheduler includes. */
60:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** #include "FreeRTOS.h"
61:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** #include "task.h"
62:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
63:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Constants required to handle interrupts. */
64:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** #define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )
65:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** #define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
66:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
67:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Constants required to handle critical sections. */
68:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** #define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
69:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** volatile unsigned portLONG ulCriticalNesting = 9999UL;
70:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
71:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /*-----------------------------------------------------------*/
72:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
73:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* ISR to handle manual context switches (from a call to taskYIELD()). */
74:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
75:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
76:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /*
77:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * The scheduler can only be started from ARM mode, hence the inclusion of this
78:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * function here.
79:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** */
80:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vPortISRStartFirstTask( void );
81:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /*-----------------------------------------------------------*/
82:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
83:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vPortISRStartFirstTask( void )
84:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** {
16 Function supports interworking.
17 @ args = 0, pretend = 0, frame = 0
18 @ frame_needed = 0, uses_anonymous_args = 0
19 @ link register save eliminated.
20 @ lr needed for prologue
21 .loc 1 87 0
85:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Simply start the scheduler. This is included here as it can only be
86:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** called from ARM mode. */
87:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** portRESTORE_CONTEXT();
22 R0, =pxCurrentTCB
23 0000 48029FE5 LDR R0, [R0]
24 0004 000090E5 LDR LR, [R0]
25 0008 00E090E5 LDR R0, =ulCriticalNesting
26 000c 40029FE5 LDMFD LR!, {R1}
27 0010 0200BEE8 STR R1, [R0]
28 0014 001080E5 LDMFD LR!, {R0}
29 0018 0100BEE8 MSR SPSR, R0
30 001c 00F069E1 LDMFD LR, {R0-R14}^
31 0020 FF7FDEE8 NOP
32 0024 0000A0E1 LDR LR, [LR, #+60]
33 0028 3CE09EE5 SUBS PC, LR, #4
34 002c 04F05EE2
35 ldr r3, .L3
36 0030 0C309FE5 ldr r3, [r3, #0]
37 0034 003093E5 ldr r3, .L3+4
38 0038 08309FE5 ldr r3, [r3, #0]
39 003c 003093E5 .loc 1 88 0
88:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** }
40 n 2
41 0040 1EFF2FE1 .L3:
42 .word ulCriticalNesting
43 .word pxCurrentTCB
44 .LFE2:
46 0048 00000000 .align 2
47 .global vPortDisableInterruptsFromThumb
49 vPortDisableInterruptsFromThumb:
50 .LFB5:
51 .loc 1 172 0
52 @ Function supports interworking.
53 @ Naked Function: prologue and epilogue provided by programmer.
89:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /*-----------------------------------------------------------*/
90:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
91:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /*
92:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * Called by portYIELD() or taskYIELD() to manually force a context switch.
93:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** *
94:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * When a context switch is performed from the task level the saved task
95:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * context is made to look as if it occurred from within the tick ISR. This
96:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * way the same restore context function can be used when restoring the context
97:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * saved from the ISR or that saved from a call to vPortYieldProcessor.
98:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** */
99:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vPortYieldProcessor( void )
100:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** {
101:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Within an IRQ ISR the link register has an offset from the true return
102:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** address, but an SWI ISR does not. Add the offset manually so the same
103:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** ISR return code can be used in both cases. */
104:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** asm volatile ( "ADD LR, LR, #4" );
105:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
106:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Perform the context switch. First save the context of the current task. */
107:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** portSAVE_CONTEXT();
108:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
109:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Find the highest priority task that is ready to run. */
110:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** vTaskSwitchContext();
111:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
112:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* Restore the context of the new task. */
113:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** portRESTORE_CONTEXT();
114:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** }
115:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /*-----------------------------------------------------------*/
116:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
117:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /*
118:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * The ISR used for the scheduler tick depends on whether the cooperative or
119:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** * the preemptive scheduler is being used.
120:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** */
121:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
122:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** #if configUSE_PREEMPTION == 0
123:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
124:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** /* The cooperative scheduler requires a normal IRQ service routine to
125:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** simply increment the system tick. */
126:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
127:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** void vNonPreemptiveTick( void )
128:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** {
129:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** vTaskIncrementTick();
130:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** T0IR = portTIMER_MATCH_ISR_BIT;
131:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** VICVectAddr = portCLEAR_VIC_INTERRUPT;
132:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** }
133:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c ****
134:rtos/Source/portable/GCC/ARM7_LPC2000/portISR.c **** #else
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