dsp281x_xintf.c

代码用于测试dsp2812的硬件功能

//###########################################################################
//
// FILE:   DSP281x_Xintf.c;
// TITLE:   DSP281x Device External Interface Init & Support Functions.
// WRITER: ZHANG X.L.;
//
//###########################################################################

#include "DSP281x_Device.h"     // DSP281x Headerfile Include File
#include "DSP281x_Examples.h"   // DSP281x Examples Include File

//---------------------------------------------------------------------------
// InitXINTF: 
//---------------------------------------------------------------------------
// This function initializes the External Interface the state needed;
//
// Do not modify the timings of the XINTF while running from the XINTF.  Doing
// so can yield unpredictable results
//---------------------------------------------------------------------------
void InitXintf(void)
{

//#if  DSP28_F2812

    // This shows how to write to the XINTF registers.  The
    // values used here are the default state after reset.
    // Different hardware will require a different configuration.
    
    // For an example of an XINTF configuration used with the
    // F2812 eZdsp, refer to the examples/run_from_xintf project.
    
    // Any changes to XINTF timing should only be made by code
    // running outside of the XINTF. 
    
    // All Zones---------------------------------
    // Timing for all zones based on XTIMCLK = SYSCLKOUT 
    //XintfRegs.XINTCNF2.bit.XTIMCLK = 0;

	// 1/2
	XintfRegs.XINTCNF2.bit.XTIMCLK = 1;

    // No write buffering
    XintfRegs.XINTCNF2.bit.WRBUFF = 0;
    // XCLKOUT is enabled
    XintfRegs.XINTCNF2.bit.CLKOFF = 0;
    // XCLKOUT = XTIMCLK 
    //XintfRegs.XINTCNF2.bit.CLKMODE = 0;

	//  1/2;
	XintfRegs.XINTCNF2.bit.CLKMODE = 1;
    
    
    // Zone 0------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING0.bit.XWRLEAD = 2;
    XintfRegs.XTIMING0.bit.XWRACTIVE = 3;
    XintfRegs.XTIMING0.bit.XWRTRAIL = 2;
    // Zone read timing
    XintfRegs.XTIMING0.bit.XRDLEAD = 2;
    XintfRegs.XTIMING0.bit.XRDACTIVE = 3;
    XintfRegs.XTIMING0.bit.XRDTRAIL = 2;
    
    // Never double all Zone read/write lead/active/trail timing 
    XintfRegs.XTIMING0.bit.X2TIMING = 0;

    // Zone will not sample XREADY signal 
    XintfRegs.XTIMING0.bit.USEREADY = 0;
    //XintfRegs.XTIMING0.bit.READYMODE = 1;  // sample asynchronous

    // Size must be 1,1 - other values are reserved
    XintfRegs.XTIMING0.bit.XSIZE = 3;
    
    // Zone 1------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING1.bit.XWRLEAD = 2;
    XintfRegs.XTIMING1.bit.XWRACTIVE = 3;
    XintfRegs.XTIMING1.bit.XWRTRAIL = 2;
    // Zone read timing
    XintfRegs.XTIMING1.bit.XRDLEAD = 2;
    XintfRegs.XTIMING1.bit.XRDACTIVE = 3;
    XintfRegs.XTIMING1.bit.XRDTRAIL = 2;
    
    // never double all Zone read/write lead/active/trail timing 
    XintfRegs.XTIMING1.bit.X2TIMING = 0;

    // Zone will not sample XREADY signal 
    XintfRegs.XTIMING1.bit.USEREADY = 0;
    //XintfRegs.XTIMING1.bit.READYMODE = 1;  // sample asynchronous

    // Size must be 1,1 - other values are reserved
    XintfRegs.XTIMING1.bit.XSIZE = 3;

	// Not used;
/*
    // Zone 2------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING2.bit.XWRLEAD = 3;
    XintfRegs.XTIMING2.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING2.bit.XWRTRAIL = 3;
    // Zone read timing
    XintfRegs.XTIMING2.bit.XRDLEAD = 3;
    XintfRegs.XTIMING2.bit.XRDACTIVE = 7;
    XintfRegs.XTIMING2.bit.XRDTRAIL = 3;
    
    // double all Zone read/write lead/active/trail timing 
    XintfRegs.XTIMING2.bit.X2TIMING = 1;

    // Zone will sample XREADY signal 
    XintfRegs.XTIMING2.bit.USEREADY = 1;
    XintfRegs.XTIMING2.bit.READYMODE = 1;  // sample asynchronous

    // Size must be 1,1 - other values are reserved
    XintfRegs.XTIMING2.bit.XSIZE = 3;
*/

    // Zone 6------------------------------------
	// Use FPGA as the zone 6;
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING6.bit.XWRLEAD = 2;
    XintfRegs.XTIMING6.bit.XWRACTIVE = 3;
    XintfRegs.XTIMING6.bit.XWRTRAIL = 2;
    // Zone read timing
    XintfRegs.XTIMING6.bit.XRDLEAD = 2;
    XintfRegs.XTIMING6.bit.XRDACTIVE = 3;
    XintfRegs.XTIMING6.bit.XRDTRAIL = 2;
    
    // Never double all Zone read/write lead/active/trail timing 
    XintfRegs.XTIMING6.bit.X2TIMING = 0;
//  XintfRegs.XTIMING6.bit.X2TIMING = 1;//double

    // Zone will not sample XREADY signal 
    XintfRegs.XTIMING6.bit.USEREADY = 0;
    //XintfRegs.XTIMING6.bit.READYMODE = 1;  // sample asynchronous

    // Size must be 1,1 - other values are reserved
    XintfRegs.XTIMING6.bit.XSIZE = 3;

	// Not used;
/*
    // Zone 7------------------------------------
    // When using ready, ACTIVE must be 1 or greater
    // Lead must always be 1 or greater
    // Zone write timing
    XintfRegs.XTIMING7.bit.XWRLEAD = 3;
    XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
    XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
    // Zone read timing
    XintfRegs.XTIMING7.bit.XRDLEAD = 3;
    XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
    XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
    
    // double all Zone read/write lead/active/trail timing 
    XintfRegs.XTIMING7.bit.X2TIMING = 1;

    // Zone will sample XREADY signal 
    XintfRegs.XTIMING7.bit.USEREADY = 1;
    XintfRegs.XTIMING7.bit.READYMODE = 1;  // sample asynchronous

    // Size must be 1,1 - other values are reserved
    XintfRegs.XTIMING7.bit.XSIZE = 3;
*/
    // Bank switching
    // Add additional BCYC cycles 
    // when ever switching from Zone 1 to another Zone.  
    // This will help avoid bus contention.
    XintfRegs.XBANK.bit.BANK = 1;
    XintfRegs.XBANK.bit.BCYC = 2;

   //Force a pipeline flush to ensure that the write to 
   //the last register configured occurs before returning.  
   asm(" RPT #8 || NOP"); 
    
//#endif
}

//---------------------------------------------------------------------------
//Suppose the FPGA at the DSP2812's XINTF ZONE 6(0x10 0000-0x18 000);
//Communicate with the FPGA through the XINTF;
//---------------------------------------------------------------------------
//Write a data to the FPGA;
//---------------------------------------------------------------------------
void WriteBus(Uchar FAddr,Uint16 FData)
{
	Uint16 *pWData;
	pWData = (Uint16 *)(FAddr + 0x100000);
	*pWData = FData;
/*
	*((Uint16 *)(FAddr + 0x100000)) = FData;
*/
}

//---------------------------------------------------------------------------
//Read a data needed from the FPGA ;
//---------------------------------------------------------------------------
Uint16 ReadBus(Uchar FAddr)
{
	Uint16 *pRData;
	Uint16 FData;
	pRData = (Uint16 *)(FAddr + 0x100000);
	FData = *pRData;
	return( FData );
/*
	return( *((Uint16 *)(FAddr + 0x100000)) );
*/
}
	
//===========================================================================
// No more.
//===========================================================================