📄 uncachedbuffer.h
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#ifndef UNCACHEDBUFFER_H#define UNCACHEDBUFFER_H#include "PoolableMemory.h"//#define NO_UNCACHED_BUFFERSnamespace oxsemi{ class UnCachedBuffer : public PoolableMemory { private: static const int CACHE_CONTROL_BIT = 31; public: static PoolableMemory* NewInstance( unsigned long size, unsigned char bufferAlignmentPowerOf2) { return new UnCachedBuffer(size, bufferAlignmentPowerOf2); } static const unsigned long CACHE_CONTROL_MASK = 1UL << CACHE_CONTROL_BIT; /** * @param pointer An unsigned char* pointing to the memory to be * tested to determine whether it is in a cached or uncached * region of the CPU's address space */ static bool IsUnCachedPointer(unsigned char* pointer); /** * Convert the passed pointer to SDRAM memory within the CPU's * uncached region into a pointer to the same memory within the CPU's * cached region. The CPU's cached region will correspond the the * address space as seen by hardware devices. Thus this method takes * the uncached address which is only valid for CPU accesses to the * pointed-to SDRAM and converts it into an address that can be used * by both the CPU for cached accesses to the SDRAM and all other * hardware devices * * @param uncachedPointer A unsigned char* pointing to SDRAM * within the CPU's uncached region * @return An unsigned char* pointing to SDRAM within the CPU's cached * region */ static unsigned char* TranslateUncachedToHardwareAccessible(unsigned char* uncachedPointer); static const unsigned char* TranslateUncachedToHardwareAccessible(const unsigned char* uncachedPointer); /** * Convert the passed pointer to SDRAM memory within the CPU's * cached region into a pointer to the same memory within the CPU's * uncached region. * * @param cachedPointer A unsigned char* pointing to SDRAM * within the CPU's cached region * @return An unsigned char* pointing to SDRAM within the CPU's * uncached region */ static unsigned char* TranslateCachedToUncached(unsigned char* cachedPointer); static const unsigned char* TranslateCachedToUncached(const unsigned char* cachedPointer); UnCachedBuffer( unsigned long bufferSizeBytes, unsigned char bufferAlignmentPowerOf2 = 0); ~UnCachedBuffer(); /** * @return A unsigned char* pointing to the memory buffer within the * CPU's uncached region */ unsigned char* GetBuffer(); /** * @return An unsigned long holding the actual size of the buffer * that was allocated to allow for adjustment to the required * alignment boundary */ unsigned long GetSize() const; /** * @return An unsigned long holding the size of the buffer that was * requested when the CTOR was invoked */ unsigned long GetRequestedSize() const; /** * Convert the encapsulated pointer to SDRAM memory within the CPU's * uncached region into a pointer to the same memory within the CPU's * cached region. The CPU's cached region will correspond the the * address space as seen by hardware devices. Thus this method takes * the uncached address which is only valid for CPU accesses to the * pointed-to SDRAM and converts it into an address that can be used * by both the CPU for cached accesses to the SDRAM and all other * hardware devices */ unsigned char* TranslateToHardwareAccessible(); private: unsigned char* uncachedAlignedMemory_; unsigned char* rawMemory_; unsigned long rawSize_; unsigned long requestedSize_; UnCachedBuffer(const UnCachedBuffer&); UnCachedBuffer& operator=(const UnCachedBuffer&); }; inline bool UnCachedBuffer::IsUnCachedPointer(unsigned char* pointer) {#ifdef NO_UNCACHED_BUFFERS return false;#else#if (defined OXSEMI_HAS_MPU) || (defined OXSEMI_HAS_MMU) return reinterpret_cast<unsigned long>(pointer) & CACHE_CONTROL_MASK;#else return false;#endif // (defined OXSEMI_HAS_MPU) || (defined OXSEMI_HAS_MMU)#endif //NO_UNCACHED_BUFFERS } inline unsigned char* UnCachedBuffer::TranslateUncachedToHardwareAccessible(unsigned char* uncachedPointer) {#ifdef NO_UNCACHED_BUFFERS return uncachedPointer;#else#if (defined OXSEMI_HAS_MPU) || (defined OXSEMI_HAS_MMU) unsigned long pointer = reinterpret_cast<unsigned long>(uncachedPointer); return reinterpret_cast<unsigned char*>(pointer &= ~CACHE_CONTROL_MASK);#else return uncachedPointer;#endif // (defined OXSEMI_HAS_MPU) || (defined OXSEMI_HAS_MMU)#endif //NO_UNCACHED_BUFFERS } inline const unsigned char* UnCachedBuffer::TranslateUncachedToHardwareAccessible(const unsigned char* uncachedPointer) { return TranslateUncachedToHardwareAccessible(const_cast<unsigned char*>(uncachedPointer)); } inline unsigned char* UnCachedBuffer::TranslateCachedToUncached(unsigned char* cachedPointer) {#ifdef NO_UNCACHED_BUFFERS return cachedPointer;#else#if (defined OXSEMI_HAS_MPU) || (defined OXSEMI_HAS_MMU) unsigned long pointer = reinterpret_cast<unsigned long>(cachedPointer); return reinterpret_cast<unsigned char*>(pointer |= CACHE_CONTROL_MASK);#else return cachedPointer;#endif // (defined OXSEMI_HAS_MPU) || (defined OXSEMI_HAS_MMU)#endif //NO_UNCACHED_BUFFERS } inline const unsigned char* UnCachedBuffer::TranslateCachedToUncached(const unsigned char* cachedPointer) { return TranslateCachedToUncached(const_cast<unsigned char*>(cachedPointer)); } inline unsigned char* UnCachedBuffer::GetBuffer() { return uncachedAlignedMemory_; } inline unsigned long UnCachedBuffer::GetSize() const { return rawSize_; } inline unsigned long UnCachedBuffer::GetRequestedSize() const { return requestedSize_; } inline unsigned char* UnCachedBuffer::TranslateToHardwareAccessible() { return TranslateUncachedToHardwareAccessible(uncachedAlignedMemory_); }}#endif
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