smsc9118.c

SMSC NET controller 9218 driver software

#define PHY_ANEG_ADV_100H_	((WORD)0x80)
#define PHY_ANEG_ADV_100F_	((WORD)0x100)
#define PHY_ANEG_ADV_SPEED_	((WORD)0x1E0)

#define PHY_ANEG_LPA	((DWORD)5U)
#define PHY_ANEG_LPA_ASYMP_		((WORD)0x0800)
#define PHY_ANEG_LPA_SYMP_		((WORD)0x0400)
#define PHY_ANEG_LPA_100FDX_	((WORD)0x0100)
#define PHY_ANEG_LPA_100HDX_	((WORD)0x0080)
#define PHY_ANEG_LPA_10FDX_		((WORD)0x0040)
#define PHY_ANEG_LPA_10HDX_		((WORD)0x0020)

#define PHY_MODE_CTRL_STS		((DWORD)17)	// Mode Control/Status Register
	#define MODE_CTRL_STS_FASTRIP_		((WORD)0x4000U)
	#define MODE_CTRL_STS_EDPWRDOWN_	((WORD)0x2000U)
	#define MODE_CTRL_STS_LOWSQEN_		((WORD)0x0800U)
	#define MODE_CTRL_STS_MDPREBP_		((WORD)0x0400U)
	#define MODE_CTRL_STS_FARLOOPBACK_	((WORD)0x0200U)
	#define MODE_CTRL_STS_FASTEST_		((WORD)0x0100U)
	#define MODE_CTRL_STS_REFCLKEN_		((WORD)0x0010U)
	#define MODE_CTRL_STS_PHYADBP_		((WORD)0x0008U)
	#define MODE_CTRL_STS_FORCE_G_LINK_	((WORD)0x0004U)
	#define MODE_CTRL_STS_ENERGYON_		((WORD)0x0002U)

#define SPECIAL_CTRL_STS                ((DWORD)27)
	#define SPECIAL_CTRL_STS_OVRRD_AMDIX_   ((WORD)0x8000U)
	#define SPECIAL_CTRL_STS_AMDIX_ENABLE_  ((WORD)0x4000U)
	#define SPECIAL_CTRL_STS_AMDIX_STATE_   ((WORD)0x2000U)

#define PHY_INT_SRC			((DWORD)29)
#define PHY_INT_SRC_ENERGY_ON_			((WORD)0x0080U)
#define PHY_INT_SRC_ANEG_COMP_			((WORD)0x0040U)
#define PHY_INT_SRC_REMOTE_FAULT_		((WORD)0x0020U)
#define PHY_INT_SRC_LINK_DOWN_			((WORD)0x0010U)

#define PHY_INT_MASK		((DWORD)30)
#define PHY_INT_MASK_ENERGY_ON_		((WORD)0x0080U)
#define PHY_INT_MASK_ANEG_COMP_		((WORD)0x0040U)
#define PHY_INT_MASK_REMOTE_FAULT_	((WORD)0x0020U)
#define PHY_INT_MASK_LINK_DOWN_		((WORD)0x0010U)

#define PHY_SPECIAL			((DWORD)31)
#define PHY_SPECIAL_SPD_	((WORD)0x001CU)
#define PHY_SPECIAL_SPD_10HALF_		((WORD)0x0004U)
#define PHY_SPECIAL_SPD_10FULL_		((WORD)0x0014U)
#define PHY_SPECIAL_SPD_100HALF_	((WORD)0x0008U)
#define PHY_SPECIAL_SPD_100FULL_	((WORD)0x0018U)

#define AMDIX_DISABLE_STRAIGHT	((WORD)0x0U)
#define AMDIX_DISABLE_CROSSOVER  	((WORD)0x01U)
#define AMDIX_ENABLE	                ((WORD)0x02U)

BOOLEAN Phy_Initialize(
	PPRIVATE_DATA privateData,
	DWORD dwPhyAddress,
	DWORD dwLinkMode);
void Phy_SetLink(PPRIVATE_DATA privateData,
				 DWORD dwLinkRequest);
WORD Phy_GetRegW(
	PPRIVATE_DATA privateData,
	DWORD dwRegIndex,
	VL_KEY keyCode);
void Phy_SetRegW(
	PPRIVATE_DATA privateData,
	DWORD dwRegIndex,
	WORD wVal,
	VL_KEY keyCode);
void Phy_UpdateLinkMode(
	PPRIVATE_DATA privateData);
void Phy_GetLinkMode(
	PPRIVATE_DATA privateData,
	VL_KEY keyCode);
void Phy_CheckLink(unsigned long ptr);
void Phy_SetAutoMdixSts(PPRIVATE_DATA privateData,
				 WORD wAutoMdixSts);
void Phy_GetAutoMdixSts(PPRIVATE_DATA privateData);





TIME_SPAN Gpt_FreeRunCompare(DWORD time1,DWORD time2);
void Gpt_ScheduleInterrupt(PPRIVATE_DATA privateData,TIME_SPAN timeSpan);
void Gpt_CancelInterrupt(PPRIVATE_DATA privateData);
void Gpt_CancelCallBack(
	PPRIVATE_DATA privateData,
	void (*callBackFunction)(PPRIVATE_DATA privateData));
void Gpt_ScheduleCallBack(
	PPRIVATE_DATA privateData,
	void (*callBackFunction)(PPRIVATE_DATA privateData),
	DWORD callBackTime);//100uS units relative to now
BOOLEAN Gpt_HandleInterrupt(
	PPRIVATE_DATA privateData,DWORD dwIntSts);
void GptCB_RxCompleteMulticast(PPRIVATE_DATA privateData);
void GptCB_RestartBurst(PPRIVATE_DATA privateData);
void GptCB_MeasureRxThroughput(PPRIVATE_DATA privateData);

void Tx_Initialize(
	PPRIVATE_DATA privateData,
	DWORD dwTxDmaCh,
	DWORD dwTxDmaThreshold);
void Tx_SendSkb(
	PPRIVATE_DATA privateData,
	struct sk_buff *skb);
BOOLEAN Tx_HandleInterrupt(
	PPRIVATE_DATA privateData,DWORD dwIntSts);

void Tx_StopQueue(
	PPRIVATE_DATA privateData,DWORD dwSource);
void Tx_WakeQueue(
	PPRIVATE_DATA privateData,DWORD dwSource);

static DWORD Tx_GetTxStatusCount(
	PPRIVATE_DATA privateData);
static DWORD Tx_CompleteTx(
	PPRIVATE_DATA privateData);
void Tx_UpdateTxCounters(
	PPRIVATE_DATA privateData);

void Tx_CompleteDma(
	PPRIVATE_DATA privateData);

void CalculateTxChecksumOffset(
	struct sk_buff *skb,
	int *csum_start_offset);

/*

void CalculateTxChecksumOffset2(
	BYTE *bCoalesceBuf,
	struct sk_buff *skb,
	int *csum_start_offset);

*/


void rkdump(unsigned char *p, unsigned short len);	

void Rx_Initialize(
	PPRIVATE_DATA privateData,
	DWORD dwRxDmaCh,
	DWORD dwDmaThreshold);

void Rx_CompleteMulticastUpdate (PPRIVATE_DATA privateData);
static void Rx_HandleOverrun(PPRIVATE_DATA privateData);
static void Rx_HandOffSkb(
	PPRIVATE_DATA privateData,
	struct sk_buff *skb);
static DWORD Rx_PopRxStatus(
	PPRIVATE_DATA privateData);
void Rx_CountErrors(PPRIVATE_DATA privateData,DWORD dwRxStatus);
void Rx_FastForward(PPRIVATE_DATA privateData,DWORD dwDwordCount);
void Rx_ProcessPackets(PPRIVATE_DATA privateData);
void Rx_BeginMulticastUpdate (PPRIVATE_DATA privateData);

unsigned long Rx_TaskletParameter=0;

void Rx_ProcessPacketsTasklet(unsigned long data);
DECLARE_TASKLET(Rx_Tasklet,Rx_ProcessPacketsTasklet,0);

#ifdef LINUX_2_6_OR_NEWER
int Smsc9118_rx_poll(struct net_device *dev,int * budget);
#endif

BOOLEAN RxStop_HandleInterrupt(
	PPRIVATE_DATA privateData,
	DWORD dwIntSts);
BOOLEAN Rx_HandleInterrupt(
	PPRIVATE_DATA privateData,
	DWORD dwIntSts);
static DWORD Rx_Hash(BYTE addr[6]);

void Rx_SetMulticastList(
	struct net_device *dev);
void Rx_ReceiverOff(
	PPRIVATE_DATA privateData);
void Rx_ReceiverOn(
	PPRIVATE_DATA privateData, VL_KEY callerKeyCode);


void Eeprom_EnableAccess(PPRIVATE_DATA privateData);
void Eeprom_DisableAccess(PPRIVATE_DATA privateData);

BOOLEAN Eeprom_IsMacAddressLoaded(PPRIVATE_DATA privateData);
BOOLEAN Eeprom_IsBusy(PPRIVATE_DATA privateData);
BOOLEAN Eeprom_Timeout(PPRIVATE_DATA privateData);

BOOLEAN Eeprom_ReadLocation(
	PPRIVATE_DATA privateData,BYTE address, BYTE * data);
BOOLEAN Eeprom_EnableEraseAndWrite(
	PPRIVATE_DATA privateData);
BOOLEAN Eeprom_DisableEraseAndWrite(
	PPRIVATE_DATA privateData);
BOOLEAN Eeprom_WriteLocation(
	PPRIVATE_DATA privateData,BYTE address,BYTE data);
BOOLEAN Eeprom_EraseAll(
	PPRIVATE_DATA privateData);
BOOLEAN Eeprom_Reload(
	PPRIVATE_DATA privateData);

BOOLEAN Eeprom_SaveMacAddress(
	PPRIVATE_DATA privateData,
	DWORD dwHi16,DWORD dwLo32);


#define OLD_REGISTERS(privData) (((privData->dwIdRev)==0x01180000UL)&& \
								 ((privData->dwFpgaRev)>=0x01)&& \
								 ((privData->dwFpgaRev)<=0x25))

extern volatile DWORD g_GpioSetting;
extern DWORD debug_mode;
#define GP_0	(0x01UL)
#define GP_1	(0x02UL)
#define GP_2	(0x04UL)
#define GP_3	(0x08UL)
#define GP_4	(0x10UL)
#define GP_OFF  (0x00UL)
#define GP_ISR	GP_OFF
#define GP_RX	GP_OFF
#define GP_TX	GP_OFF
#define GP_BEGIN_MULTICAST_UPDATE		GP_OFF
#define GP_COMPLETE_MULTICAST_UPDATE	GP_OFF

#define SET_GPIO(gpioBit)					\
if(debug_mode&0x04UL) {						\
	g_GpioSetting|=gpioBit;					\
	Lan_SetRegDW(GPIO_CFG,g_GpioSetting);	\
}

#define CLEAR_GPIO(gpioBit)					\
if(debug_mode&0x04UL) {						\
	g_GpioSetting&=(~gpioBit);				\
	Lan_SetRegDW(GPIO_CFG,g_GpioSetting);	\
}

#define PULSE_GPIO(gpioBit,count)	\
if(debug_mode&0x04UL) {				\
	DWORD pulseNum=0;				\
	/*make first pulse longer */	\
	SET_GPIO(gpioBit);				\
	while(pulseNum<count) {			\
		SET_GPIO(gpioBit);			\
		CLEAR_GPIO(gpioBit);		\
		pulseNum++;					\
	}								\
}
#ifdef USE_LED1_WORK_AROUND
volatile DWORD g_GpioSettingOriginal;
#endif

BOOLEAN Lan_Initialize(
	PPRIVATE_DATA privateData,DWORD dwIntCfg,
	DWORD dwTxFifSz,DWORD dwAfcCfg);
void Lan_EnableInterrupt(PPRIVATE_DATA privateData,DWORD dwIntEnMask);
void Lan_DisableInterrupt(PPRIVATE_DATA privateData,DWORD dwIntEnMask);
void Lan_EnableIRQ(PPRIVATE_DATA privateData);
void Lan_DisableIRQ(PPRIVATE_DATA privateData);
void Lan_SetIntDeas(PPRIVATE_DATA privateData,DWORD dwIntDeas);
void Lan_SetTDFL(PPRIVATE_DATA privateData,BYTE level);
void Lan_SetTSFL(PPRIVATE_DATA privateData,BYTE level);
void Lan_SetRDFL(PPRIVATE_DATA privateData,BYTE level);
void Lan_SetRSFL(PPRIVATE_DATA privateData,BYTE level);

void Lan_SignalSoftwareInterrupt(PPRIVATE_DATA privateData);
BOOLEAN Lan_HandleSoftwareInterrupt(PPRIVATE_DATA privateData,DWORD dwIntSts);

void Lan_ShowRegs(PPRIVATE_DATA privateData);

#include "ioctl_118.h"

DWORD lan_base=0x0UL;
MODULE_PARM(lan_base,"i");
MODULE_PARM_DESC(lan_base,"Base Address of LAN9118, (default: choosen by platform code)");

DWORD bus_width=0UL;
MODULE_PARM(bus_width,"i");
MODULE_PARM_DESC(bus_width,"Force bus width of 16 or 32 bits, default: autodetect");

DWORD link_mode=0x7FUL;
MODULE_PARM(link_mode,"i");
MODULE_PARM_DESC(link_mode,"Set Link speed and Duplex, 1=10HD,2=10FD,4=100HD,8=100FD,default=0xF");

WORD AutoMdix=0x3U;
MODULE_PARM(AutoMdix,"i");
MODULE_PARM_DESC(AutoMdix,"Set Auto-MDIX state, 0=StraightCable,1=CrossOver,2=Enable AMDIX,3=controlled by Strap");

DWORD irq=PLATFORM_IRQ;
MODULE_PARM(irq,"i");
MODULE_PARM_DESC(irq,"Force use of specific IRQ, (default: choosen by platform code)");

DWORD int_deas=0xFFFFFFFFUL;
MODULE_PARM(int_deas,"i");
MODULE_PARM_DESC(int_deas,"Interrupt Deassertion Interval in 10uS units");

DWORD irq_pol=PLATFORM_IRQ_POL;
MODULE_PARM(irq_pol,"i");
MODULE_PARM_DESC(irq_pol,"IRQ Polarity bit, see definition of INT_CFG register");

DWORD irq_type=PLATFORM_IRQ_TYPE;
MODULE_PARM(irq_type,"i");
MODULE_PARM_DESC(irq_type,"IRQ Buffer Type bit, see definition of INT_CFG register");

DWORD rx_dma=PLATFORM_RX_DMA;
MODULE_PARM(rx_dma,"i");
MODULE_PARM_DESC(rx_dma,"Receiver DMA Channel, 255=find available channel, 256=use PIO");

DWORD tx_dma=PLATFORM_TX_DMA;
MODULE_PARM(tx_dma,"i");
MODULE_PARM_DESC(tx_dma,"Transmitter DMA Channel, 255=find available channel, 256=use PIO");

DWORD dma_threshold=PLATFORM_DMA_THRESHOLD;
MODULE_PARM(dma_threshold,"i");
MODULE_PARM_DESC(dma_threshold,"Specifies the minimum packet size for DMA to be used.");

DWORD mac_addr_hi16=0xFFFFFFFFUL;
MODULE_PARM(mac_addr_hi16,"i");
MODULE_PARM_DESC(mac_addr_hi16,"Specifies the high 16 bits of the mac address");

DWORD mac_addr_lo32=0xFFFFFFFFUL;
MODULE_PARM(mac_addr_lo32,"i");
MODULE_PARM_DESC(mac_addr_lo32,"Specifies the low 32 bits of the mac address");

#ifdef USE_DEBUG
DWORD debug_mode=0x7UL;
#else
DWORD debug_mode=0x0UL;
#endif
MODULE_PARM(debug_mode,"i");
MODULE_PARM_DESC(debug_mode,"bit 0 enables trace points, bit 1 enables warning points, bit 2 enables gpios");

DWORD tx_fif_sz=0x00050000UL;
MODULE_PARM(tx_fif_sz,"i");
MODULE_PARM_DESC(tx_fif_sz,"Specifies TX_FIF_SZ of the HW_CFG register");

DWORD afc_cfg=0xFFFFFFFFUL;
MODULE_PARM(afc_cfg,"i");
MODULE_PARM_DESC(afc_cfg,"Specifies the setting for the AFC_CFG register");

//DWORD tasklets=1UL;
//MODULE_PARM(tasklets,"i");
//MODULE_PARM_DESC(tasklets,"non-zero== use tasklets for receiving packets, zero==receive packets in ISR");

#define PROCESSING_MODE_IDLE	(0UL)
#define PROCESSING_MODE_TASKLET	(1UL)
#define PROCESSING_MODE_NAPI	(2UL)


DWORD rx_mode=PROCESSING_MODE_NAPI;
MODULE_PARM(rx_mode,"i");
MODULE_PARM_DESC(rx_mode,"0==use ISR, 1==use Rx Tasklet, 2==use NAPI");

#ifdef LINUX_2_6_OR_NEWER
DWORD napi_weight=4UL;
MODULE_PARM(napi_weight,"i");
MODULE_PARM_DESC(napi_weight,"The weight value to use if NAPI is used");
#endif



DWORD phy_addr=0xFFFFFFFFUL;
MODULE_PARM(phy_addr,"i");
MODULE_PARM_DESC(phy_addr,"phy_addr, 0xFFFFFFFF=use interal phy, 0-31=use external phy with specified address, else autodetect external phy addr");

DWORD max_throughput=0xFFFFFFFFUL;
MODULE_PARM(max_throughput,"i");
MODULE_PARM_DESC(max_throughput,"See readme.txt");

DWORD max_packet_count=0xFFFFFFFFUL;
MODULE_PARM(max_packet_count,"i");
MODULE_PARM_DESC(max_packet_count,"See Readme.txt");

DWORD packet_cost=0xFFFFFFFFUL;
MODULE_PARM(packet_cost,"i");
MODULE_PARM_DESC(packet_cost,"See Readme.txt");

DWORD burst_period=0xFFFFFFFFUL;
MODULE_PARM(burst_period,"i");
MODULE_PARM_DESC(burst_period,"See Readme.txt");

DWORD max_work_load=0xFFFFFFFFUL;
MODULE_PARM(max_work_load,"i");
MODULE_PARM_DESC(max_work_load,"See Readme.txt");

BOOLEAN Scatter_gather=TRUE;
MODULE_PARM(Scatter_gather,"bool");
MODULE_PARM_DESC(Scatter_gather,"Enable Scatter Gather");

BOOLEAN tx_Csum=TRUE;
MODULE_PARM(tx_Csum,"bool");
MODULE_PARM_DESC(tx_Csum,"Enable Tx Hardware Checksum Offload");

BOOLEAN rx_Csum=TRUE;
MODULE_PARM(rx_Csum,"bool");