serial.hif

来自「基于FPGA的串口通信」· HIF 代码 · 共 1,035 行

Version 6.0 Build 178 04/27/2006 SJ Full Version
35
1731
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
altsyncram_cfg1
# storage
db|serial.(5).cnf
db|serial.(5).cnf
# case_insensitive
# source_file
db|altsyncram_cfg1.tdf
a483ddfcaa377dbb3bb9cec7f08ccd28
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# end
# entity
altsyncram
# storage
db|serial.(4).cnf
db|serial.(4).cnf
# case_insensitive
# source_file
d:|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
5
PARAMETER_DEC
USR
NUMWORDS_B
32
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_cfg1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
d:|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
d:|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
d:|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
d:|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
d:|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
d:|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
d:|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
d:|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
d:|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
d:|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# end
# entity
ram1
# storage
db|serial.(3).cnf
db|serial.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
ram1.vhd
9e4410482af7872b8190185d2f72e54a
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(data)
7 downto 0
PARAMETER_STRING
USR
 constraint(rdaddress)
4 downto 0
PARAMETER_STRING
USR
 constraint(wraddress)
4 downto 0
PARAMETER_STRING
USR
 constraint(q)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
ram1:ram
}
# end
# entity
altsyncram
# storage
db|serial.(6).cnf
db|serial.(6).cnf
# case_insensitive
# source_file
d:|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
5
PARAMETER_DEC
USR
NUMWORDS_B
32
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_06h1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
d:|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
d:|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
d:|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
d:|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
d:|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
d:|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
d:|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
d:|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
d:|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
d:|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
ram1:ram|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_06h1
# storage
db|serial.(7).cnf
db|serial.(7).cnf
# case_insensitive
# source_file
db|altsyncram_06h1.tdf
041336029da23f9cd5134d23d9eca5
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# hierarchies {
ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated
}
# end
# entity
serial
# storage
db|serial.(0).cnf
db|serial.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
serial.vhd
d753749a1fba337027d113a1ddf3ea
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
tx
# storage
db|serial.(8).cnf
db|serial.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
tx.vhd
9e3761d8c868b388bc028f26442e153
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(txd_data)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
tx:tx1
}
# end
# entity
rx
# storage
db|serial.(2).cnf
db|serial.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rx.vhd
8f95b07fce4ae284a8ece2e88721b95
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(rxd_data)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
rx:rx1
}
# end
# entity
fenpin
# storage
db|serial.(1).cnf
db|serial.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fenpin.vhd
76a27154738ba325d8771092308e92a
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
period
110101010110
PARAMETER_BIN
DEF
}
# hierarchies {
fenpin:fp
}
# end
# complete