fenpin.vhd

基于FPGA的串口通信

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity fenpin is
generic (period:std_logic_vector(11 downto 0):="110101010110");

port(
     clk32,rstn,read_en,write_en,read_end,write_end:in std_logic;
     clk_read,clk_write:out std_logic);
end fenpin;

architecture behav0 of fenpin is
type states is(txd_start,txd_wait,rxd_start,rxd_sample,rxd_wait);--------数据总线几种状态	
signal state1:states:=txd_wait;
signal state2:states:=rxd_wait;
signal reg1,reg2:std_logic_vector(11 downto 0);

---------------------------------------------------------------
  begin
   process(clk32,rstn)
     begin
       if(rstn='0')then
         state1<=txd_wait;
         state2<=rxd_wait;
       elsif(clk32'event and clk32='1')then
         case state1 is
            when txd_wait=>
               if(write_en = '1')then
                  state1 <= txd_start;
               else
                  state1 <= txd_wait;
               end if;
            when txd_start=>
               if(write_end = '1')then
                  state1 <= txd_wait;
               else
                  state1 <= txd_start;
               end if;
            when others =>
               state1 <= txd_wait;
          end case;
          case state2 is
            when rxd_wait=>
               if(read_en = '1')then
                  state2 <= rxd_start;
               else
                  state2 <= rxd_wait;
               end if;
            when rxd_start=>
               if(reg1 = period)then
                  state2 <= rxd_sample;
               else
                  state2 <= rxd_start;
               end if;
            when rxd_sample=>
               if(read_end = '1')then
                  state2 <= rxd_wait;
               else
                  state2 <= rxd_sample;
               end if;
            when others =>
               state2 <= rxd_wait;
          end case;
       end if;
    end process;
---------------------------------------------------------------
   process(clk32,rstn)
     begin
       if(rstn='0')then
         reg1<="000000000000";
         reg2<="000000000000";
         clk_read<='0';
         clk_write<='0';
       elsif(clk32'event and clk32='1')then
         case state1 is
            when txd_wait=>
                 clk_write<='0'; 
                 reg1<="000000000000";  
            when txd_start=>
               reg1<= reg1 + 1;
               if(reg1 = period)then
                  reg1<="000000000000";
               end if;
               if (reg1 ="000000000000")then
                  clk_write<='1';
               else
                  clk_write<='0'; 
               end if;
            when others =>
                clk_write<='0'; 
                reg1<="000000000000";  
          end case;
          case state2 is
            when rxd_wait=>
                 clk_read<='0'; 
                 reg2<='0'&period(11 downto 7)&"000000";  
            when rxd_start=>
                 reg2<= reg2 + 1;
               if(reg2 = period)then
                  reg2<="000000000000";
                  clk_read<='1';
               else
                  clk_read<='0'; 
               end if;
            when rxd_sample=>
                reg2<= reg2 + 1;
               if(reg2 = period)then
                  reg2<="000000000000";
                  clk_read<='1';
               else
                  clk_read<='0'; 
               end if;
            when others =>
               clk_read<='0'; 
               reg2<='0'&period(11 downto 7)&"000000"; 
          end case;
       end if;
    end process;
------------------------------------------------------------------------
end behav0;