serial.map.rpt

基于FPGA的串口通信

; Source assignments for tx:tx1          ;
+----------------+-------+------+--------+
; Assignment     ; Value ; From ; To     ;
+----------------+-------+------+--------+
; POWER_UP_LEVEL ; High  ; -    ; state1 ;
+----------------+-------+------+--------+


+------------------------------------------------------------------------------------------------+
; Source assignments for ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------+
; Assignment                      ; Value              ; From ; To                               ;
+---------------------------------+--------------------+------+----------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                ;
+---------------------------------+--------------------+------+----------------------------------+


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: fenpin:fp ;
+----------------+--------------+------------------------+
; Parameter Name ; Value        ; Type                   ;
+----------------+--------------+------------------------+
; period         ; 110101010110 ; Binary                 ;
+----------------+--------------+------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ram1:ram|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+--------------------------------+
; Parameter Name                     ; Value           ; Type                           ;
+------------------------------------+-----------------+--------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                        ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                     ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                   ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                   ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                 ;
; OPERATION_MODE                     ; DUAL_PORT       ; Untyped                        ;
; WIDTH_A                            ; 8               ; Integer                        ;
; WIDTHAD_A                          ; 5               ; Integer                        ;
; NUMWORDS_A                         ; 32              ; Integer                        ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                        ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                        ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                        ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                        ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                        ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                        ;
; WIDTH_B                            ; 8               ; Integer                        ;
; WIDTHAD_B                          ; 5               ; Integer                        ;
; NUMWORDS_B                         ; 32              ; Integer                        ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                        ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                        ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                        ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                        ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                        ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                        ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                        ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                        ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                        ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                        ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                        ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                        ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                        ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                        ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                        ;
; BYTE_SIZE                          ; 8               ; Untyped                        ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                        ;
; INIT_FILE                          ; UNUSED          ; Untyped                        ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                        ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                        ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                        ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                        ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                        ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                        ;
; DEVICE_FAMILY                      ; Cyclone         ; Untyped                        ;
; CBXI_PARAMETER                     ; altsyncram_06h1 ; Untyped                        ;
+------------------------------------+-----------------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Mar 05 15:45:44 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serial -c serial
Info: Found 2 design units, including 1 entities, in source file ram1.vhd
    Info: Found design unit 1: ram1-SYN
    Info: Found entity 1: ram1
Info: Found 2 design units, including 1 entities, in source file tx.vhd
    Info: Found design unit 1: tx-behav2
    Info: Found entity 1: tx
Info: Found 2 design units, including 1 entities, in source file rx.vhd
    Info: Found design unit 1: rx-behav1
    Info: Found entity 1: rx
Info: Found 2 design units, including 1 entities, in source file fenpin.vhd
    Info: Found design unit 1: fenpin-behav0
    Info: Found entity 1: fenpin
Info: Found 2 design units, including 1 entities, in source file serial.vhd
    Info: Found design unit 1: serial-behav
    Info: Found entity 1: serial
Info: Elaborating entity "serial" for the top level hierarchy
Info: Elaborating entity "fenpin" for hierarchy "fenpin:fp"
Info: Elaborating entity "rx" for hierarchy "rx:rx1"
Info: Elaborating entity "tx" for hierarchy "tx:tx1"
Info: Elaborating entity "ram1" for hierarchy "ram1:ram"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "ram1:ram|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "ram1:ram|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_06h1.tdf
    Info: Found entity 1: altsyncram_06h1
Info: Elaborating entity "altsyncram_06h1" for hierarchy "ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated"
Info: Duplicate registers merged to single register
    Info: Duplicate register "wenlock" merged to single register "ram_rclk"
    Info: Duplicate register "ren" merged to single register "ram_wclk"
Info: State machine "|serial|fenpin:fp|state2" contains 5 states
Info: State machine "|serial|fenpin:fp|state1" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|serial|fenpin:fp|state2"
Info: Encoding result for state machine "|serial|fenpin:fp|state2"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "fenpin:fp|state2.txd_start"
        Info: Encoded state bit "fenpin:fp|state2.rxd_sample"
        Info: Encoded state bit "fenpin:fp|state2.rxd_start"
        Info: Encoded state bit "fenpin:fp|state2.txd_wait"
        Info: Encoded state bit "fenpin:fp|state2.rxd_wait"
    Info: State "|serial|fenpin:fp|state2.rxd_wait" uses code string "00000"
    Info: State "|serial|fenpin:fp|state2.txd_wait" uses code string "00011"
    Info: State "|serial|fenpin:fp|state2.rxd_start" uses code string "00101"
    Info: State "|serial|fenpin:fp|state2.rxd_sample" uses code string "01001"
    Info: State "|serial|fenpin:fp|state2.txd_start" uses code string "10001"
Info: Selected Auto state machine encoding method for state machine "|serial|fenpin:fp|state1"
Info: Encoding result for state machine "|serial|fenpin:fp|state1"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "fenpin:fp|state1.rxd_wait"
        Info: Encoded state bit "fenpin:fp|state1.rxd_sample"
        Info: Encoded state bit "fenpin:fp|state1.rxd_start"
        Info: Encoded state bit "fenpin:fp|state1.txd_start"
        Info: Encoded state bit "fenpin:fp|state1.txd_wait"
    Info: State "|serial|fenpin:fp|state1.txd_wait" uses code string "00000"
    Info: State "|serial|fenpin:fp|state1.txd_start" uses code string "00011"
    Info: State "|serial|fenpin:fp|state1.rxd_start" uses code string "00101"
    Info: State "|serial|fenpin:fp|state1.rxd_sample" uses code string "01001"
    Info: State "|serial|fenpin:fp|state1.rxd_wait" uses code string "10001"
Info: Registers with preset signals will power-up high
Info: Implemented 126 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 1 output pins
    Info: Implemented 114 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Mar 05 15:45:47 2009
    Info: Elapsed time: 00:00:04