serial.vhd

基于FPGA的串口通信

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity serial is
port(clk32,rstn:in std_logic;
     rxd:in std_logic;
     txd:out std_logic);
end serial;

architecture behav of serial is

component fenpin
port(
     clk32,rstn,read_en,write_en,read_end,write_end:in std_logic;
     clk_read,clk_write:out std_logic);
end component;

component rx
port(clk32,rclk,rstn,rxd:in std_logic;
     rxd_data:out std_logic_vector(7 downto 0);
     read_en,read_end:out std_logic  --------一帧数据接收标志
     );
end component;

component tx
port(clk32,wclk,rstn,wen:in std_logic;
     txd_data:in std_logic_vector(7 downto 0);
     write_en,write_end,txd:out std_logic  --------一帧数据标志
     );
end component;

component ram1
PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		rdclock		: IN STD_LOGIC ;
		wraddress		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		wrclock		: IN STD_LOGIC ;
		wren		: IN STD_LOGIC  := '1';
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;

signal rclk,wclk,ram_rclk,ram_wclk:std_logic;
signal ren,wen,renlock,wenlock,r_en,r_end,w_en,w_end:std_logic;
signal raddr,waddr:std_logic_vector(4 downto 0);
signal rdata,wdata:std_logic_vector(7 downto 0);

begin
   fp:fenpin port map(clk32,rstn,r_en,w_en,r_end,w_end,rclk,wclk);
   rx1:rx port map(clk32,rclk,rstn,rxd,wdata,r_en,r_end);  
   --tx1:tx port map(clk32,wclk,rstn,ren,wdata,w_en,w_end,txd);
   tx1:tx port map(clk32,wclk,rstn,wen,rdata,w_en,w_end,txd);
   ram:ram1 port map(wdata,raddr,ram_rclk,waddr,ram_wclk,'1',rdata);
---------------------------------------------------------------
   process(clk32,rstn)
     begin
       if(rstn='0')then
         ren<='0';
         renlock<='0';
         ram_wclk<='0';
         waddr<="00000";
       elsif(clk32'event and clk32='1')then
         ram_wclk<= r_end;
         ren <=r_end;
         renlock<= ren;
         if (renlock='1')then
            waddr<=waddr+1;
         end if;
       end if; 
   end process;
---------------------------------------------------------------
   process(clk32,rstn)
     begin
       if(rstn='0')then
         wen<='0';
         wenlock<='0';
         raddr<="00000";
         ram_rclk<='0';
       elsif(clk32'event and clk32='1')then
         ram_rclk<=renlock;
         wenlock<=renlock;
         wen<=wenlock;
         if (wenlock ='1')then
            raddr<= raddr + 1;
         end if;
       end if; 
   end process;
---------------------------------------------------------------
end behav;