serial.tan.summary

基于FPGA的串口通信

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.936 ns
From           : rxd
To             : rx:rx1|read_en
From Clock     : --
To Clock       : clk32
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.609 ns
From           : tx:tx1|txd
To             : txd
From Clock     : clk32
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.575 ns
From           : rxd
To             : rx:rx1|data_reg[9]
From Clock     : --
To Clock       : clk32
Failed Paths   : 0

Type           : Clock Setup: 'clk32'
Slack          : N/A
Required Time  : None
Actual Time    : 88.25 MHz ( period = 11.332 ns )
From           : ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4
To             : tx:tx1|data_reg[8]
From Clock     : clk32
To Clock       : clk32
Failed Paths   : 0

Type           : Clock Hold: 'clk32'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : raddr[4]
To             : ram1:ram|altsyncram:altsyncram_component|altsyncram_06h1:auto_generated|ram_block1a0~portb_address_reg4
From Clock     : clk32
To Clock       : clk32
Failed Paths   : 18

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 18

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