at91_tl16c554.h

嵌入式 linux 扩展串口 驱动 测试程序

/*----------------------------------------------------------
**	linux/drivers/at91/at91_tl16c554.h
**		
**
**	Copyright (C) 2006 Hyesco Technology Co.,Ltd
**
**	Author: casiawu <[e-mail]>
**
**	History:
**
**	2006.6   casiawu  <[e-mail]>
**               Original version
**---------------------------------------------------------*/
#ifndef __AT91_TL16C554_H_
#define __AT91_TL16C554_H_

/******************************************************/
/*	片选地址定义                                      */
/******************************************************/

#define TL16C554_BASE_ADDR_USA5 0x80000060
#define TL16C554_BASE_ADDR_USB6 0x80000080
#define TL16C554_BASE_ADDR_USC7 0x800000a0
#define TL16C554_BASE_ADDR_USD8 0x800000c0

#define TL16C554_PIO5          (0x1<<0)
#define TL16C554_PIO6          (0x1<<1)
#define TL16C554_PIO7          (0x1<<2)
#define TL16C554_PIO8          (0x1<<3)

#define  VA_SIZE                 0x10

static int TL16C554_VA_BASE_ADDR5 ;
static int TL16C554_VA_BASE_ADDR6;
static int TL16C554_VA_BASE_ADDR7;
static int TL16C554_VA_BASE_ADDR8;


/******************************************************/
/*	特殊功能寄存器地址定义                            */
/******************************************************/
	
#define RBR 0X00    //receiver-buffer register            
#define THR 0X00	  //transmitter-holding register
#define DLL 0X00
#define DLM 0X02
#define IER 0X02		//interrupt-enable register
#define FCR 0X04		//FIFO-control register
#define IIR 0X04		//interrupt-identification register
#define LCR 0X06		//line-control register
#define MCR 0X08		//modem-control register
#define LSR 0X0a		//line-status register
#define MSR 0X0c		//modem-status register
#define SCR 0X0e  	//scratchpad register

typedef struct _TL16C554_USART {
	volatile unsigned char	 US_RBR_THR_DLL; 	   // receiver/trans-buffer register/Dll Register
        volatile unsigned char   US_SCRATCH0;
	volatile unsigned char	 US_DLM_IER; 	       // DLL register / interrupt-enable register 
        volatile unsigned char   US_SCRATCH1;
	volatile unsigned char	 US_FCR_IIR; 	       // FIFO-control register/interrupt-identification register
        volatile unsigned char   US_SCRATCH2;
	volatile unsigned char	 US_LCR;             // line-control register
        volatile unsigned char   US_SCRATCH3;
	volatile unsigned char	 US_MCR; 	           // modem-control register
        volatile unsigned char   US_SCRATCH4;
	volatile unsigned char	 US_LSR; 	           // line-status register
        volatile unsigned char   US_SCRATCH5;
	volatile unsigned char	 US_MSR; 	           // modem-status register
        volatile unsigned char   US_SCRATCH6;
	volatile unsigned char	 US_SCR; 	           // scratchpad register
} TL16C554_USART, *TL16C554PS_USART;

//波特率设置
#define TL16C554_CLOCK                 8000000
#define BAND                           115200
#define QUTO_DEFAULT                   (TL16C554_CLOCK/BAND/16)

//寄存器配置
#define  LCR_CONFIG_DEFAULT              0x03             //8 Bytes, 1 Stop bit, No Parity
#define  MCR_CONFIG_DEFAULT              0x08             //set local loopback mode
#define  FCR_CONFIG_DEFULT		           0x87             //ENABLE FIFO,CLEAR FIFO(receive and transmit FIFO), Triggle Level = 8(Bytes)

#define  AT91C_US_CHRL                     0x3 
#define  AT91C_US_NBSTOP                  (0x1<<2) 
#define  AT91C_US_PAR                     (0x3<<2)

#define  TL16C554_US_CHRL_5_BITS           0x0
#define  TL16C554_US_CHRL_6_BITS           0x1
#define  TL16C554_US_CHRL_7_BITS           0x2
#define  TL16C554_US_CHRL_8_BITS           0x3

#define  TL16C554_US_NBSTOP_2_BIT         (0x1<<2)

#define  TL16C554_US_PAR_NONE             (0x0<<3)
#define  TL16C554_US_PAR_ODD              (0x1<<3)
#define  TL16C554_US_PAR_EVEN             (0x3<<3)

#define  TL16C554_US_RXRDY                ( 0x1 <<  0) // (USART) RXTX Ready
#define  TL16C554_US_OVRE                 ( 0x1 <<  1) // (USART) OVER Err
#define  TL16C554_US_PARE                 ( 0x1 <<  2) // (USART) PAR Err
#define  TL16C554_US_FRAME                ( 0x1 <<  3) // (USART) FRAME Err
#define  TL16C554_US_BREAKI               ( 0x1 <<  4) // (USART) Break Interrupt
#define  TL16C554_US_THRE                 ( 0x1 <<  5) // (USART) Trans Holding register empty
#define  TL16C554_US_TEMT                 ( 0x1 <<  6) // (USART) Trans register empty
#define  TL16C554_US_REFIFOE              ( 0x1 <<  7) // (USART) Receive Fifo Err

#define  TL16C554_DIS                     0x00
#define  TL16C554_EN                      0x87

#define  TL16C554_RX_FULL                 (0x1<<0)
#define  TL16C554_TX_EMPTY                (0x1<<1)            
#define  TL16C554_LINE_INTER_             (0x1<<2)
#define  TL16C554_MODEM_INTER             (0x1<<3)

#define  TL16C554_IIR_NoInter               0x1
#define  TL16C554_IIR_ReLineStat            0x6
#define  TL16C554_IIR_ReDataAvail           0x4
#define  TL16C554_IIR_ReTimeOut             0xc
#define  TL16C554_IIR_THRE                  0x2
#define  TL16C554_IIR_ModemStat             0x0

#define  TL16C554_US_RIIC                   0x4
#define  TL16C554_US_DSRIC                  0x2
#define  TL16C554_US_DCDIC                  0x8
#define  TL16C554_US_DCD                    0x80
#define  TL16C554_US_CTSIC                  0x0                 
#define  TL16C554_US_CTS                    0x10
#define  TL16C554_US_RI                     0x40
#define  TL16C554_US_DSR                    0x20

#define  TL16C554_US_SETBRK                 (0x1<<6)
#define  TL16C554_US_DTREN                  (0x1<<0)
#define  TL16C554_US_RTSEN                  (0x1<<1)


#define  TL16C554_NR_FIFO                   16
#define  TL16C554_NR_UART                   4
#define  TL16C554_UART_MAP		              { 5, 6, 7, 8 }	   /* ttyS5, ..., ttyS8 */

#endif  //__AT91_TL16C554_H_