sfr64.h

瑞萨单片机测试程序:P9口流水灯测试,低电平点亮发光二极管.

union byte_def	int1ic_addr;
#define		int1ic			int1ic_addr.byte

#define		ilvl0_int1ic	int1ic_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_int1ic	int1ic_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_int1ic	int1ic_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_int1ic		int1ic_addr.bit.b3			/* Interrupt request bit */
#define		pol_int1ic		int1ic_addr.bit.b4			/* Polarity select bit */

/*------------------------------------------------------
	INT2 receive interrupt control register
------------------------------------------------------*/
union byte_def	int2ic_addr;
#define		int2ic			int2ic_addr.byte

#define		ilvl0_int2ic	int2ic_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_int2ic	int2ic_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_int2ic	int2ic_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_int2ic		int2ic_addr.bit.b3			/* Interrupt request bit */
#define		pol_int2ic		int2ic_addr.bit.b4			/* Polarity select bit */

/*------------------------------------------------------
	DMA2 interrupt control register
------------------------------------------------------*/
union byte_def	dm2ic_addr;
#define		dm2ic			dm2ic_addr.byte

#define		ilvl0_dm2ic		dm2ic_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_dm2ic		dm2ic_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_dm2ic		dm2ic_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_dm2ic		dm2ic_addr.bit.b3			/* Interrupt request bit */

/*------------------------------------------------------
	DMA3 interrupt control register
------------------------------------------------------*/
union byte_def	dm3ic_addr;
#define		dm3ic			dm3ic_addr.byte

#define		ilvl0_dm3ic		dm3ic_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_dm3ic		dm3ic_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_dm3ic		dm3ic_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_dm3ic		dm3ic_addr.bit.b3			/* Interrupt request bit */

/*------------------------------------------------------
	UART5 BUS collision detection interrupt control register
------------------------------------------------------*/
union byte_def	u5bcnic_addr;
#define		u5bcnic			u5bcnic_addr.byte

#define		ilvl0_u5bcnic	u5bcnic_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_u5bcnic	u5bcnic_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_u5bcnic	u5bcnic_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_u5bcnic		u5bcnic_addr.bit.b3			/* Interrupt request bit */

/*------------------------------------------------------
	UART5 transmit interrupt control register
------------------------------------------------------*/
union byte_def	s5tic_addr;
#define		s5tic			s5tic_addr.byte

#define		ilvl0_s5tic		s5tic_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_s5tic		s5tic_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_s5tic		s5tic_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_s5tic		s5tic_addr.bit.b3			/* Interrupt request bit */

/*------------------------------------------------------
	UART5 receive interrupt control register
------------------------------------------------------*/
union byte_def	s5ric_addr;
#define		s5ric			s5ric_addr.byte

#define		ilvl0_s5ric		s5ric_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_s5ric		s5ric_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_s5ric		s5ric_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_s5ric		s5ric_addr.bit.b3			/* Interrupt request bit */

/*------------------------------------------------------
	UART6 BUS collision detection interrupt control register
------------------------------------------------------*/
union byte_def	u6bcnic_addr;
#define		u6bcnic			u6bcnic_addr.byte

#define		ilvl0_u6bcnic	u6bcnic_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_u6bcnic	u6bcnic_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_u6bcnic	u6bcnic_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_u6bcnic		u6bcnic_addr.bit.b3			/* Interrupt request bit */

/*------------------------------------------------------
	UART6 transmit interrupt control register
------------------------------------------------------*/
union byte_def	s6tic_addr;
#define		s6tic			s6tic_addr.byte

#define		ilvl0_s6tic		s6tic_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_s6tic		s6tic_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_s6tic		s6tic_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_s6tic		s6tic_addr.bit.b3			/* Interrupt request bit */

/*------------------------------------------------------
	UART6 receive interrupt control register
------------------------------------------------------*/
union byte_def	s6ric_addr;
#define		s6ric			s6ric_addr.byte

#define		ilvl0_s6ric		s6ric_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_s6ric		s6ric_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_s6ric		s6ric_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_s6ric		s6ric_addr.bit.b3			/* Interrupt request bit */

/*------------------------------------------------------
	UART7 BUS collision detection interrupt control register
------------------------------------------------------*/
union byte_def	u7bcnic_addr;
#define		u7bcnic			u7bcnic_addr.byte

#define		ilvl0_u7bcnic	u7bcnic_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_u7bcnic	u7bcnic_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_u7bcnic	u7bcnic_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_u7bcnic		u7bcnic_addr.bit.b3			/* Interrupt request bit */

/*------------------------------------------------------
	UART5 transmit interrupt control register
------------------------------------------------------*/
union byte_def	s7tic_addr;
#define		s7tic			s7tic_addr.byte

#define		ilvl0_s7tic		s7tic_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_s7tic		s7tic_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_s7tic		s7tic_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_s7tic		s7tic_addr.bit.b3			/* Interrupt request bit */

/*------------------------------------------------------
	UART5 receive interrupt control register
------------------------------------------------------*/
union byte_def	s7ric_addr;
#define		s7ric			s7ric_addr.byte

#define		ilvl0_s7ric		s7ric_addr.bit.b0			/* Interrupt priority level select bit */
#define		ilvl1_s7ric		s7ric_addr.bit.b1			/* Interrupt priority level select bit */
#define		ilvl2_s7ric		s7ric_addr.bit.b2			/* Interrupt priority level select bit */
#define		ir_s7ric		s7ric_addr.bit.b3			/* Interrupt request bit */

/*------------------------------------------------------
	 DMA0 source pointer 32 bit
------------------------------------------------------*/
union dword_def	sar0_addr;
#define		sar0			sar0_addr.dword
#define		sar0l			sar0_addr.byte.low			/* DMA0 source pointer low  8 bit */
#define		sar0m			sar0_addr.byte.mid			/* DMA0 source pointer mid  8 bit */
#define		sar0h			sar0_addr.byte.high			/* DMA0 source pointer high 8 bit */

/*------------------------------------------------------
	 DMA0 destination pointer 32 bit
------------------------------------------------------*/
union dword_def	dar0_addr;
#define		dar0			dar0_addr.dword
#define		dar0l			dar0_addr.byte.low			/* DMA0 destination pointer low  8 bit */
#define		dar0m			dar0_addr.byte.mid			/* DMA0 destination pointer mid  8 bit */
#define		dar0h			dar0_addr.byte.high			/* DMA0 destination pointer high 8 bit */

/*------------------------------------------------------
	 DMA0 transfer counter 16 bit
------------------------------------------------------*/
union word_def	tcr0_addr;
#define		tcr0			tcr0_addr.word
#define		tcr0l			tcr0_addr.byte.low			/* DMA0 transfer counter low  8 bit */
#define		tcr0h			tcr0_addr.byte.high			/* DMA0 transfer counter high 8 bit */

/*------------------------------------------------------
	 DMA0 control register
------------------------------------------------------*/
union byte_def	dm0con_addr;
#define		dm0con			dm0con_addr.byte

#define		dmbit_dm0con	dm0con_addr.bit.b0			/* Transfer unit bit select bit */
#define		dmasl_dm0con	dm0con_addr.bit.b1			/* Repeat transfer mode select bit */
#define		dmas_dm0con		dm0con_addr.bit.b2			/* DMA request bit */
#define		dmae_dm0con		dm0con_addr.bit.b3			/* DMA enable bit */
#define		dsd_dm0con		dm0con_addr.bit.b4			/* Source address direction select bit */
#define		dad_dm0con		dm0con_addr.bit.b5			/* Destination address direction select bit */

/*------------------------------------------------------
	 DMA1 source pointer 32 bit
------------------------------------------------------*/
union dword_def	sar1_addr;
#define		sar1			sar1_addr.dword
#define		sar1l			sar1_addr.byte.low			/* DMA1 source pointer low  8 bit */
#define		sar1m			sar1_addr.byte.mid			/* DMA1 source pointer mid  8 bit */
#define		sar1h			sar1_addr.byte.high			/* DMA1 source pointer high 8 bit */

/*------------------------------------------------------
	 DMA1 destination pointer 32 bit
------------------------------------------------------*/
union dword_def	dar1_addr;
#define		dar1			dar1_addr.dword
#define		dar1l			dar1_addr.byte.low			/* DMA1 destination pointer low  8 bit */
#define		dar1m			dar1_addr.byte.mid			/* DMA1 destination pointer mid  8 bit */
#define		dar1h			dar1_addr.byte.high			/* DMA1 destination pointer high 8 bit */

/*------------------------------------------------------
	 DMA1 transfer counter 16 bit
------------------------------------------------------*/
union word_def	tcr1_addr;
#define		tcr1			tcr1_addr.word
#define		tcr1l			tcr1_addr.byte.low			/* DMA1 transfer counter low  8 bit */
#define		tcr1h			tcr1_addr.byte.high			/* DMA1 transfer counter high 8 bit */

/*------------------------------------------------------
	 DMA1 control register
------------------------------------------------------*/
union byte_def	dm1con_addr;
#define		dm1con			dm1con_addr.byte

#define		dmbit_dm1con	dm1con_addr.bit.b0			/* Transfer unit bit select bit */
#define		dmasl_dm1con	dm1con_addr.bit.b1			/* Repeat transfer mode select bit */
#define		dmas_dm1con		dm1con_addr.bit.b2			/* DMA request bit */
#define		dmae_dm1con		dm1con_addr.bit.b3			/* DMA enable bit */
#define		dsd_dm1con		dm1con_addr.bit.b4			/* Source address direction select bit */
#define		dad_dm1con		dm1con_addr.bit.b5			/* Destination address direction select bit */

/*------------------------------------------------------
	 DMA2 source pointer 32 bit
------------------------------------------------------*/
union dword_def	sar2_addr;
#define		sar2			sar2_addr.dword
#define		sar2l			sar2_addr.byte.low			/* DMA1 source pointer low  8 bit */
#define		sar2m			sar2_addr.byte.mid			/* DMA1 source pointer mid  8 bit */
#define		sar2h			sar2_addr.byte.high			/* DMA1 source pointer high 8 bit */

/*------------------------------------------------------
	 DMA2 destination pointer 32 bit
------------------------------------------------------*/
union dword_def	dar2_addr;
#define		dar2			dar2_addr.dword
#define		dar2l			dar2_addr.byte.low			/* DMA1 destination pointer low  8 bit */
#define		dar2m			dar2_addr.byte.mid			/* DMA1 destination pointer mid  8 bit */
#define		dar2h			dar2_addr.byte.high			/* DMA1 destination pointer high 8 bit */

/*------------------------------------------------------
	 DMA2 transfer counter 16 bit
------------------------------------------------------*/
union word_def	tcr2_addr;
#define		tcr2			tcr2_addr.word
#define		tcr2l			tcr2_addr.byte.low			/* DMA2 transfer counter low  8 bit */
#define		tcr2h			tcr2_addr.byte.high			/* DMA2 transfer counter high 8 bit */

/*------------------------------------------------------
	 DMA2 control register
------------------------------------------------------*/
union byte_def	dm2con_addr;
#define		dm2con			dm2con_addr.byte

#define		dmbit_dm2con	dm2con_addr.bit.b0			/* Transfer unit bit select bit */
#define		dmasl_dm2con	dm2con_addr.bit.b1			/* Repeat transfer mode select bit */
#define		dmas_dm2con		dm2con_addr.bit.b2			/* DMA request bit */
#define		dmae_dm2con		dm2con_addr.bit.b3			/* DMA enable bit */
#define		dsd_dm2con		dm2con_addr.bit.b4			/* Source address direction select bit */
#define		dad_dm2con		dm2con_addr.bit.b5			/* Destination address direction select bit */

/*------------------------------------------------------
	 DMA3 source pointer 32 bit
------------------------------------------------------*/
union dword_def	sar3_addr;
#define		sar3			sar3_addr.dword
#define		sar3l			sar3_addr.byte.low			/* DMA1 source pointer low  8 bit */
#define		sar3m			sar3_addr.byte.mid			/* DMA1 source pointer mid  8 bit */
#define		sar3h			sar3_addr.byte.high			/* DMA1 source pointer high 8 bit */

/*------------------------------------------------------
	 DMA3 destination pointer 32 bit
------------------------------------------------------*/
union dword_def	dar3_addr;
#define		dar3			dar3_addr.dword
#define		dar3l			dar3_addr.byte.low			/* DMA1 destination pointer low  8 bit */
#define		dar3m			dar3_addr.byte.mid			/* DMA1 destination pointer mid  8 bit */
#define		dar3h			dar3_addr.byte.high			/* DMA1 destination pointer high 8 bit */

/*------------------------------------------------------
	 DMA3 transfer counter 16 bit
------------------------------------------------------*/
union word_def	tcr3_addr;
#define		tcr3			tcr3_addr.word
#define		tcr3l			tcr3_addr.byte.low			/* DMA3 transfer counter low  8 bit */
#define		tcr3h			tcr3_addr.byte.high			/* DMA3 transfer counter high 8 bit */

/*------------------------------------------------------
	 DMA3 control register
------------------------------------------------------*/
union byte_def	dm3con_addr;
#define		dm3con			dm3con_addr.byte

#define		dmbit_dm3con	dm3con_addr.bit.b0			/* Transfer unit bit select bit */
#define		dmasl_dm3con	dm3con_addr.bit.b1			/* Repeat transfer mode select bit */
#define		dmas_dm3con		dm3con_addr.bit.b2			/* DMA request bit */
#define		dmae_dm3con		dm3con_addr.bit.b3			/* DMA enable bit */
#define		dsd_dm3con		dm3con_addr.bit.b4			/* Source address direction s