📄 sfr64.h
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char b16:1;
char b17:1;
char b18:1;
char b19:1;
} bit;
struct {
char low; /* low 8 bit */
char mid; /* mid 8 bit */
char high; /* high 8 bit */
char nc; /* non use */
} byte;
unsigned long dword;
};
/********************************************************
* Definition of SFR *
********************************************************/
/*-------------------------------------------------------
Processor mode register 0
-------------------------------------------------------*/
union byte_def pm0_addr;
#define pm0 pm0_addr.byte
#define pm00 pm0_addr.bit.b0 /* Processor mode bit */
#define pm01 pm0_addr.bit.b1 /* Processor mode bit */
#define pm02 pm0_addr.bit.b2 /* R/W mode select bit */
#define pm03 pm0_addr.bit.b3 /* Software reset bit */
#define pm04 pm0_addr.bit.b4 /* Multiplexed bus space select bit */
#define pm05 pm0_addr.bit.b5 /* Multiplexed bus space select bit */
#define pm06 pm0_addr.bit.b6 /* Port P4_0 to P4_3 function select bit */
#define pm07 pm0_addr.bit.b7 /* BCLK output disable bit */
/*------------------------------------------------------
Processor mode register 1
------------------------------------------------------*/
union byte_def pm1_addr;
#define pm1 pm1_addr.byte
#define pm10 pm1_addr.bit.b0 /* CS2 area switching bit */
#define pm11 pm1_addr.bit.b1 /* Port P3_4 to P3_7 function select bit */
#define pm12 pm1_addr.bit.b2 /* Watch dog timer function select bit */
#define pm13 pm1_addr.bit.b3 /* Intermal reserved area expansion bit */
#define pm14 pm1_addr.bit.b4 /* Memory area expansion bit */
#define pm15 pm1_addr.bit.b5 /* Memory area expansion bit */
#define pm17 pm1_addr.bit.b7 /* Wait bit */
/*------------------------------------------------------
System clock control register 0
------------------------------------------------------*/
union byte_def cm0_addr;
#define cm0 cm0_addr.byte
#define cm00 cm0_addr.bit.b0 /* Clock output function select bit */
#define cm01 cm0_addr.bit.b1 /* Clock output function select bit */
#define cm02 cm0_addr.bit.b2 /* WAIT peripheral function clock stop bit */
#define cm03 cm0_addr.bit.b3 /* Xcin-Xcout drive capacity select bit */
#define cm04 cm0_addr.bit.b4 /* Port Xc select bit */
#define cm05 cm0_addr.bit.b5 /* Main clock stop bit */
#define cm06 cm0_addr.bit.b6 /* Main clock division select bit 0 */
#define cm07 cm0_addr.bit.b7 /* System clock select bit */
/*------------------------------------------------------
System clock control register 1
------------------------------------------------------*/
union byte_def cm1_addr;
#define cm1 cm1_addr.byte
#define cm10 cm1_addr.bit.b0 /* All clock stop control bit */
#define cm11 cm1_addr.bit.b1 /* System clock select bit */
#define cm14 cm1_addr.bit.b4 /* 125 kHz on-chip oscillator stop bit */
#define cm15 cm1_addr.bit.b5 /* Xin-Xout drive capacity select bit */
#define cm16 cm1_addr.bit.b6 /* Main clock division select bit 1 */
#define cm17 cm1_addr.bit.b7 /* Main clock division select bit 1 */
/*------------------------------------------------------
Chip select control register
------------------------------------------------------*/
union byte_def csr_addr;
#define csr csr_addr.byte
#define cs0 csr_addr.bit.b0 /* CS0~ output enable bit */
#define cs1 csr_addr.bit.b1 /* CS1~ output enable bit */
#define cs2 csr_addr.bit.b2 /* CS2~ output enable bit */
#define cs3 csr_addr.bit.b3 /* CS3~ output enable bit */
#define cs0w csr_addr.bit.b4 /* CS0~ wait bit */
#define cs1w csr_addr.bit.b5 /* CS1~ wait bit */
#define cs2w csr_addr.bit.b6 /* CS2~ wait bit */
#define cs3w csr_addr.bit.b7 /* CS3~ wait bit */
/*------------------------------------------------------
Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define prcr prcr_addr.byte
#define prc0 prcr_addr.bit.b0 /* Protect bit 0 */
#define prc1 prcr_addr.bit.b1 /* Protect bit 1 */
#define prc2 prcr_addr.bit.b2 /* Protect bit 2 */
#define prc3 prcr_addr.bit.b3 /* Protect bit 3 */
#define prc6 prcr_addr.bit.b6 /* Protect bit 6 */
/*------------------------------------------------------
Data bank register
------------------------------------------------------*/
union byte_def dbr_addr;
#define dbr dbr_addr.byte
#define ofs dbr_addr.bit.b2 /* Offset bit */
#define bsr0 dbr_addr.bit.b3 /* Bank select bit 0 */
#define bsr1 dbr_addr.bit.b4 /* Bank select bit 1 */
#define bsr2 dbr_addr.bit.b5 /* Bank select bit 2 */
/*------------------------------------------------------
Oscillation stop detection register
------------------------------------------------------*/
union byte_def cm2_addr;
#define cm2 cm2_addr.byte
#define cm20 cm2_addr.bit.b0 /* Oscillation stop detection bit */
#define cm21 cm2_addr.bit.b1 /* Main clock switch bit */
#define cm22 cm2_addr.bit.b2 /* Oscillation stop detection status */
#define cm23 cm2_addr.bit.b3 /* Clock monitor bit */
#define cm27 cm2_addr.bit.b7 /* Operation select bit(when an oscillation stop is detected) */
/*------------------------------------------------------
Program 2 Area Control Register
------------------------------------------------------*/
union byte_def prg2c_addr;
#define prg2c prg2c_addr.byte
#define prg2c0 prg2c_addr.bit.b0 /* Program ROM 2 disable bit */
/*------------------------------------------------------
Peripheral clock select register
------------------------------------------------------*/
union byte_def pclkr_addr;
#define pclkr pclkr_addr.byte
#define pclk0 pclkr_addr.bit.b0 /* TimerA,B clock select bit */
#define pclk1 pclkr_addr.bit.b1 /* SI/O clock select bit */
/*------------------------------------------------------
Clock prescaler reset flag
------------------------------------------------------*/
union byte_def cpsrf_addr;
#define cpsrf cpsrf_addr.byte
#define cpsr cpsrf_addr.bit.b7 /* Clock prescaler reset flag */
/*------------------------------------------------------
Reset Source Determine Flag
------------------------------------------------------*/
union byte_def rstfr_addr;
#define rstfr rstfr_addr.byte
#define cwr rstfr_addr.bit.b0 /* Cold start-up / warm start determine flag */
/*------------------------------------------------------
Power supply detection register 1
------------------------------------------------------*/
union byte_def vcr1_addr;
#define vcr1 vcr1_addr.byte
#define vc13 vcr1_addr.bit.b3 /* Power supply down monitor flag */
/*------------------------------------------------------
Power supply detection register 2
------------------------------------------------------*/
union byte_def vcr2_addr;
#define vcr2 vcr2_addr.byte
#define vc25 vcr2_addr.bit.b5 /* Voltage detection 0 enable bit */
#define vc27 vcr2_addr.bit.b7 /* Power supply down monitor bit */
/*------------------------------------------------------
Chip select expansion control register
------------------------------------------------------*/
union byte_def cse_addr;
#define cse cse_addr.byte
#define cse00w cse_addr.bit.b0 /* CS0~ wait expansion bit */
#define cse01w cse_addr.bit.b1 /* CS0~ wait expansion bit */
#define cse10w cse_addr.bit.b2 /* CS1~ wait expansion bit */
#define cse11w cse_addr.bit.b3 /* CS1~ wait expansion bit */
#define cse20w cse_addr.bit.b4 /* CS2~ wait expansion bit */
#define cse21w cse_addr.bit.b5 /* CS2~ wait expansion bit */
#define cse30w cse_addr.bit.b6 /* CS3~ wait expansion bit */
#define cse31w cse_addr.bit.b7 /* CS3~ wait expansion bit */
/*------------------------------------------------------
PLL control register 0
------------------------------------------------------*/
union byte_def plc0_addr;
#define plc0 plc0_addr.byte
#define plc00 plc0_addr.bit.b0 /* PLL multiplying factor select bit */
#define plc01 plc0_addr.bit.b1 /* PLL multiplying factor select bit */
#define plc02 plc0_addr.bit.b2 /* PLL multiplying factor select bit */
#define plc04 plc0_addr.bit.b4 /* Reference frequency counter set bit */
#define plc05 plc0_addr.bit.b5 /* Reference frequency counter set bit */
#define plc07 plc0_addr.bit.b7 /* Operation enable bit */
/*------------------------------------------------------
Processor mode register 2
------------------------------------------------------*/
union byte_def pm2_addr;
#define pm2 pm2_addr.byte
#define pm20 pm2_addr.bit.b0 /* Specifying wait when accessing SFR at PLL operation */
#define pm21 pm2_addr.bit.b1 /* System clock protective bit */
#define pm24 pm2_addr.bit.b4 /* P8_5 / NMI function select bit */
#define pm25 pm2_addr.bit.b5 /* D4INT clock provide enable bit */
/*------------------------------------------------------
Power supply down detection register
------------------------------------------------------*/
union byte_def d4int_addr;
#define d4int d4int_addr.byte
#define d40 d4int_addr.bit.b0 /* Power supply down detection interrupt enable bit */
#define d41 d4int_addr.bit.b1 /* STOP mode deactivation control bit */
#define d42 d4int_addr.bit.b2 /* Power supply change detection flag */
#define d43 d4int_addr.bit.b3 /* WDT overflow detect flag */
#define df0 d4int_addr.bit.b4 /* Sampling clock select bit */
#define df1 d4int_addr.bit.b5 /* Sampling clock select bit */
/*------------------------------------------------------
Voltage Monitor 0 Circuit Control Register
------------------------------------------------------*/
union byte_def vw0c_addr;
#define vw0c vw0c_addr.byte
#define vw0c0 vw0c_addr.bit.b0 /* Brown-out reset enable bit */
#define vw0c1 vw0c_addr.bit.b1 /* Voltage monitor 0 digital filter RW disable mode select bit */
#define vw0f0 vw0c_addr.bit.b4 /* Sampling clock select bit */
#define vw0f1 vw0c_addr.bit.b5 /* Sampling clock select bit */
/*------------------------------------------------------
INT7 interrupt control register
------------------------------------------------------*/
union byte_def int7ic_addr;
#define int7ic int7ic_addr.byte
#define ilvl0_int7ic int7ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int7ic int7ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int7ic int7ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int7ic int7ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int7ic int7ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
INT6 interrupt control register
------------------------------------------------------*/
union byte_def int6ic_addr;
#define int6ic int6ic_addr.byte
#define ilvl0_int6ic int6ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int6ic int6ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int6ic int6ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int6ic int6ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int6ic int6ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
INT3 interrupt control register
------------------------------------------------------*/
union byte_def int3ic_addr;
#define int3ic int3ic_addr.byte
#define ilvl0_int3ic int3ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_int3ic int3ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_int3ic int3ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_int3ic int3ic_addr.bit.b3 /* Interrupt request bit */
#define pol_int3ic int3ic_addr.bit.b4 /* Polarity select bit */
/*------------------------------------------------------
Timer B5 interrupt control register
------------------------------------------------------*/
union byte_def tb5ic_addr;
#define tb5ic tb5ic_addr.byte
#define ilvl0_tb5ic tb5ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb5ic tb5ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb5ic tb5ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb5ic tb5ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
Timer B4 interrupt control register
------------------------------------------------------*/
union byte_def tb4ic_addr;
#define tb4ic tb4ic_addr.byte
#define ilvl0_tb4ic tb4ic_addr.bit.b0 /* Interrupt priority level select bit */
#define ilvl1_tb4ic tb4ic_addr.bit.b1 /* Interrupt priority level select bit */
#define ilvl2_tb4ic tb4ic_addr.bit.b2 /* Interrupt priority level select bit */
#define ir_tb4ic tb4ic_addr.bit.b3 /* Interrupt request bit */
/*------------------------------------------------------
UART1 BUS collision detection interrupt control register
------------------------------------------------------*/
union byte_def u1bcnic_addr;
#define u1bcnic u1bcnic_addr.byte
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