91x_map.h

a set or ARM9 examples by STM

#define APB_WDG_OFST       (0x0000B000) /* Offset of WDG               */
#define APB_I2C0_OFST      (0x0000C000) /* Offset of I2C0              */
#define APB_I2C1_OFST      (0x0000D000) /* Offset of I2C1              */

/*----------------------------------------------------------------------------*/
/*----------------------------- Unbuffered Mode ------------------------------*/
/*----------------------------------------------------------------------------*/

#ifndef Buffered 

/*******************************************************************************
*                  AHBAPB peripheral Unbuffered Base Address                   *
*******************************************************************************/

#define AHBAPB0_BASE           (AHB_APB_BRDG0_U)
#define AHBAPB1_BASE           (AHB_APB_BRDG1_U)

/*******************************************************************************
*                  ENET peripheral Unbuffered Base Address                     *
*******************************************************************************/

#define ENET_MAC_BASE          (AHB_ENET_MAC_U)
#define ENET_DMA_BASE          (AHB_ENET_DMA_U)

/*******************************************************************************
*                  DMA peripheral Unbuffered Base Address                      *
*******************************************************************************/

#define DMA_BASE           (AHB_DMA_U)

/*******************************************************************************
*                  EMI peripheral Unbuffered Base Address                      *
*******************************************************************************/

#define EMI_BASE           (AHB_EMI_U)    

/*******************************************************************************
*                  FMI peripheral Unbuffered Base Address                      *
*******************************************************************************/

#define FMI_BASE           (AHB_FMI_U)


#else /* Buffered */

/*----------------------------------------------------------------------------*/
/*------------------------------ Buffered Mode -------------------------------*/
/*----------------------------------------------------------------------------*/

/*******************************************************************************
*                   AHBAPB peripheral Buffered Base Address                    *
*******************************************************************************/

#define AHBAPB0_BASE           (AHB_APB_BRDG0_B)
#define AHBAPB1_BASE           (AHB_APB_BRDG1_B)

/*******************************************************************************
*                  ENET peripheral Unbuffered Base Address                     *
*******************************************************************************/

#define ENET_MAC_BASE          (AHB_ENET_MAC_B)
#define ENET_DMA_BASE          (AHB_ENET_DMA_B)

/*******************************************************************************
*                    DMA peripheral Buffered Base Address                      *
*******************************************************************************/

#define DMA_BASE           (AHB_DMA_B)

/*******************************************************************************
*                      EMI peripheral Buffered Base Address                    *
*******************************************************************************/

#define EMI_BASE           (AHB_EMI_B)

/*******************************************************************************
*                      FMI peripheral Buffered Base Address                    *
*******************************************************************************/

#define FMI_BASE           (AHB_FMI_B)

#endif /* Buffered */

/*******************************************************************************
*                          DMA channels Base Address                           *
*******************************************************************************/
#define DMA_Channel0_BASE  (DMA_BASE + AHB_DMA_Channel0_OFST)
#define DMA_Channel1_BASE  (DMA_BASE + AHB_DMA_Channel1_OFST)
#define DMA_Channel2_BASE  (DMA_BASE + AHB_DMA_Channel2_OFST)
#define DMA_Channel3_BASE  (DMA_BASE + AHB_DMA_Channel3_OFST)
#define DMA_Channel4_BASE  (DMA_BASE + AHB_DMA_Channel4_OFST)
#define DMA_Channel5_BASE  (DMA_BASE + AHB_DMA_Channel5_OFST)
#define DMA_Channel6_BASE  (DMA_BASE + AHB_DMA_Channel6_OFST)
#define DMA_Channel7_BASE  (DMA_BASE + AHB_DMA_Channel7_OFST)

/*******************************************************************************
*                     EMI Banks peripheral Base Address                        *
*******************************************************************************/

#define EMI_Bank0_BASE  (EMI_BASE + AHB_EMIB0_OFST)
#define EMI_Bank1_BASE  (EMI_BASE + AHB_EMIB1_OFST)
#define EMI_Bank2_BASE  (EMI_BASE + AHB_EMIB2_OFST)
#define EMI_Bank3_BASE  (EMI_BASE + AHB_EMIB3_OFST)

/*******************************************************************************
*                     APB0 Peripherals' Base addresses                         *
*******************************************************************************/

#define WIU_BASE           (AHBAPB0_BASE + APB_WIU_OFST)
#define TIM0_BASE          (AHBAPB0_BASE + APB_TIM0_OFST)
#define TIM1_BASE          (AHBAPB0_BASE + APB_TIM1_OFST)
#define TIM2_BASE          (AHBAPB0_BASE + APB_TIM2_OFST)
#define TIM3_BASE          (AHBAPB0_BASE + APB_TIM3_OFST)
#define GPIO0_BASE         (AHBAPB0_BASE + APB_GPIO0_OFST)
#define GPIO1_BASE         (AHBAPB0_BASE + APB_GPIO1_OFST)
#define GPIO2_BASE         (AHBAPB0_BASE + APB_GPIO2_OFST)
#define GPIO3_BASE         (AHBAPB0_BASE + APB_GPIO3_OFST)
#define GPIO4_BASE         (AHBAPB0_BASE + APB_GPIO4_OFST)
#define GPIO5_BASE         (AHBAPB0_BASE + APB_GPIO5_OFST)
#define GPIO6_BASE         (AHBAPB0_BASE + APB_GPIO6_OFST)
#define GPIO7_BASE         (AHBAPB0_BASE + APB_GPIO7_OFST)
#define GPIO8_BASE         (AHBAPB0_BASE + APB_GPIO8_OFST)
#define GPIO9_BASE         (AHBAPB0_BASE + APB_GPIO9_OFST)

/*******************************************************************************
*                      APB1 Peripherals' Base addresses                        *
*******************************************************************************/

#define RTC_BASE           (AHBAPB1_BASE + APB_RTC_OFST)
#define SCU_BASE           (AHBAPB1_BASE + APB_SCU_OFST)
#define MC_BASE            (AHBAPB1_BASE + APB_MC_OFST)
#define UART0_BASE         (AHBAPB1_BASE + APB_UART0_OFST)
#define UART1_BASE         (AHBAPB1_BASE + APB_UART1_OFST)
#define UART2_BASE         (AHBAPB1_BASE + APB_UART2_OFST)
#define SSP0_BASE          (AHBAPB1_BASE + APB_SSP0_OFST)
#define SSP1_BASE          (AHBAPB1_BASE + APB_SSP1_OFST)
#define CAN_BASE           (AHBAPB1_BASE + APB_CAN_OFST)
#define ADC_BASE           (AHBAPB1_BASE + APB_ADC_OFST)
#define WDG_BASE           (AHBAPB1_BASE + APB_WDG_OFST)
#define I2C0_BASE          (AHBAPB1_BASE + APB_I2C0_OFST)
#define I2C1_BASE          (AHBAPB1_BASE + APB_I2C1_OFST)

/*******************************************************************************
*                                IPs' declaration                              *
*******************************************************************************/

/*------------------------------ Non Debug Mode ------------------------------*/

#ifndef DEBUG

/*********************************** AHBAPB ***********************************/

#define AHBAPB0               ((AHBAPB_TypeDef *)AHBAPB0_BASE)
#define AHBAPB1               ((AHBAPB_TypeDef *)AHBAPB1_BASE)

/************************************* EMI ************************************/

#define EMI                ((EMI_TypeDef *)EMI_BASE)

/************************************* DMA ************************************/

#define DMA                ((DMA_TypeDef *)DMA_BASE)
#define DMA_Channel0       ((DMA_Channel_TypeDef *)DMA_Channel0_BASE)
#define DMA_Channel1       ((DMA_Channel_TypeDef *)DMA_Channel1_BASE)
#define DMA_Channel2       ((DMA_Channel_TypeDef *)DMA_Channel2_BASE)
#define DMA_Channel3       ((DMA_Channel_TypeDef *)DMA_Channel3_BASE)
#define DMA_Channel4       ((DMA_Channel_TypeDef *)DMA_Channel4_BASE)
#define DMA_Channel5       ((DMA_Channel_TypeDef *)DMA_Channel5_BASE)
#define DMA_Channel6       ((DMA_Channel_TypeDef *)DMA_Channel6_BASE)
#define DMA_Channel7       ((DMA_Channel_TypeDef *)DMA_Channel7_BASE)

/************************************* EMI ************************************/

#define EMI_Bank0         ((EMI_Bank_TypeDef *)EMI_Bank0_BASE)
#define EMI_Bank1         ((EMI_Bank_TypeDef *)EMI_Bank1_BASE)
#define EMI_Bank2         ((EMI_Bank_TypeDef *)EMI_Bank2_BASE)
#define EMI_Bank3         ((EMI_Bank_TypeDef *)EMI_Bank3_BASE)

/************************************* ENET_MAC ************************************/

#define ENET_MAC              ((ENET_MAC_TypeDef *)ENET_MAC_BASE)

/************************************* ENET_DMA ************************************/

#define ENET_DMA              ((ENET_DMA_TypeDef *)ENET_DMA_BASE)

/************************************* FMI ************************************/

#define FMI                ((FMI_TypeDef *)FMI_BASE)

/************************************* VIC ************************************/

#define VIC0               ((VIC_TypeDef *)VIC0_BASE)
#define VIC1               ((VIC_TypeDef *)VIC1_BASE)

/*******************************************************************************
*                              APB0 Peripherals'                               *
*******************************************************************************/
#define WIU                ((WIU_TypeDef *)WIU_BASE)
#define TIM0               ((TIM_TypeDef *)TIM0_BASE)
#define TIM1               ((TIM_TypeDef *)TIM1_BASE)
#define TIM2               ((TIM_TypeDef *)TIM2_BASE)
#define TIM3               ((TIM_TypeDef *)TIM3_BASE)
#define GPIO0              ((GPIO_TypeDef *)GPIO0_BASE)
#define GPIO1              ((GPIO_TypeDef *)GPIO1_BASE)
#define GPIO2              ((GPIO_TypeDef *)GPIO2_BASE)
#define GPIO3              ((GPIO_TypeDef *)GPIO3_BASE)
#define GPIO4              ((GPIO_TypeDef *)GPIO4_BASE)
#define GPIO5              ((GPIO_TypeDef *)GPIO5_BASE)
#define GPIO6              ((GPIO_TypeDef *)GPIO6_BASE)
#define GPIO7              ((GPIO_TypeDef *)GPIO7_BASE)
#define GPIO8              ((GPIO_TypeDef *)GPIO8_BASE)
#define GPIO9              ((GPIO_TypeDef *)GPIO9_BASE)
/*******************************************************************************
*                              APB1 Peripherals'                               *
*******************************************************************************/
#define RTC                ((RTC_TypeDef *)RTC_BASE)
#define SCU                ((SCU_TypeDef *)SCU_BASE)
#define MC                 ((MC_TypeDef *)MC_BASE)
#define UART0              ((UART_TypeDef *)UART0_BASE)
#define UART1              ((UART_TypeDef *)UART1_BASE)
#define UART2              ((UART_TypeDef *)UART2_BASE)
#define SSP0               ((SSP_TypeDef *)SSP0_BASE)
#define SSP1               ((SSP_TypeDef *)SSP1_BASE)
#define CAN                ((CAN_TypeDef *)CAN_BASE)
#define ADC                ((ADC_TypeDef *)ADC_BASE)
#define WDG                ((WDG_TypeDef *)WDG_BASE)
#define I2C0               ((I2C_TypeDef *)I2C0_BASE)
#define I2C1               ((I2C_TypeDef *)I2C1_BASE)
#define ENET_MAC           ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
#define ENET_DMA           ((ENET_DMA_TypeDef *)ENET_DMA_BASE)

#else   /* DEBUG */

/*-------------------------------- Debug Mode --------------------------------*/

EXT AHBAPB_TypeDef         *AHBAPB0;
EXT AHBAPB_TypeDef         *AHBAPB1;
EXT DMA_TypeDef            *DMA;
EXT DMA_Channel_TypeDef    *DMA_Channel0;
EXT DMA_Channel_TypeDef    *DMA_Channel1;
EXT DMA_Channel_TypeDef    *DMA_Channel2;
EXT DMA_Channel_TypeDef    *DMA_Channel3;
EXT DMA_Channel_TypeDef    *DMA_Channel4;
EXT DMA_Channel_TypeDef    *DMA_Channel5;
EXT DMA_Channel_TypeDef    *DMA_Channel6;
EXT DMA_Channel_TypeDef    *DMA_Channel7;
EXT EMI_Bank_TypeDef       *EMI_Bank0;
EXT EMI_Bank_TypeDef       *EMI_Bank1;
EXT EMI_Bank_TypeDef       *EMI_Bank2;
EXT EMI_Bank_TypeDef       *EMI_Bank3;
EXT FMI_TypeDef            *FMI;
EXT VIC_TypeDef            *VIC0;
EXT VIC_TypeDef            *VIC1;
EXT WIU_TypeDef            *WIU;
EXT TIM_TypeDef            *TIM0;
EXT TIM_TypeDef            *TIM1;
EXT TIM_TypeDef            *TIM2;
EXT TIM_TypeDef            *TIM3;
EXT GPIO_TypeDef           *GPIO0;
EXT GPIO_TypeDef           *GPIO1;
EXT GPIO_TypeDef           *GPIO2;
EXT GPIO_TypeDef           *GPIO3;
EXT GPIO_TypeDef           *GPIO4;
EXT GPIO_TypeDef           *GPIO5;
EXT GPIO_TypeDef           *GPIO6;
EXT GPIO_TypeDef           *GPIO7;
EXT GPIO_TypeDef           *GPIO8;
EXT GPIO_TypeDef           *GPIO9;
EXT RTC_TypeDef            *RTC;
EXT SCU_TypeDef            *SCU;
EXT MC_TypeDef             *MC;
EXT UART_TypeDef           *UART0;
EXT UART_TypeDef           *UART1;
EXT UART_TypeDef           *UART2;
EXT SSP_TypeDef            *SSP0;
EXT SSP_TypeDef            *SSP1;
EXT CAN_TypeDef            *CAN;
EXT ADC_TypeDef            *ADC;
EXT WDG_TypeDef            *WDG;
EXT I2C_TypeDef            *I2C0;
EXT I2C_TypeDef            *I2C1;
EXT ENET_MAC_TypeDef       *ENET_MAC;
EXT ENET_DMA_TypeDef       *ENET_DMA;


#endif  /* DEBUG */

#endif  /* __91x_MAP_H*/

/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/