startup.s

The GraphicAnimation project is a program for the AT91RM9200 using Atmel AT91RM9200-EK Evaluation B

;//       <o1.8..11>  TDF: Data Float Time <0-15>
;//       <o1.12>     BAT: Byte Access Type  
;//                     <0=> Chip Select line connected to  8-bit wide (2 or 4) devices
;//                     <1=> Chip Select line connected to 16-bit wide device
;//       <o1.13..14> DBW: Data Bus Width
;//                     <0=> Reserved     <1=> 16-bit
;//                     <2=> 8-bit        <3=> Reserved
;//       <o1.15>     DRP: Data Read Protocol
;//                     <0=> Standard Read Protocol is used
;//                     <1=> Early Read Protocol is used
;//       <o1.16..17> ACSS: Address to Chip Select Setup
;//                     <0=> Standard, asserted at the bigining of access and deasserted at the end
;//                     <1=> One cycle less at the begining and the end of access
;//                     <2=> Two cycle less at the begining and the end of access
;//                     <3=> Three cycle less at the begining and the end of access
;//       <o1.24..26> RWSETUP: Read and Write Signal Setup Time <0-7>
;//       <o1.28..30> RWHOLD: Read and Write Signal Hold Time <0-7>
;//     </e>
SMC_CSR4_SETUP  EQU     0x00000000
SMC_CSR4_Val    EQU     0x00000000

;//     <e> Chip Select Register 5 (SMC_CSR5)
;//       <o1.0..6>   NWS: Number of Wait States <0-127>
;//       <o1.7>      WSEN: Wait State Enabled
;//       <o1.8..11>  TDF: Data Float Time <0-15>
;//       <o1.12>     BAT: Byte Access Type  
;//                     <0=> Chip Select line connected to  8-bit wide (2 or 4) devices
;//                     <1=> Chip Select line connected to 16-bit wide device
;//       <o1.13..14> DBW: Data Bus Width
;//                     <0=> Reserved     <1=> 16-bit
;//                     <2=> 8-bit        <3=> Reserved
;//       <o1.15>     DRP: Data Read Protocol
;//                     <0=> Standard Read Protocol is used
;//                     <1=> Early Read Protocol is used
;//       <o1.16..17> ACSS: Address to Chip Select Setup
;//                     <0=> Standard, asserted at the bigining of access and deasserted at the end
;//                     <1=> One cycle less at the begining and the end of access
;//                     <2=> Two cycle less at the begining and the end of access
;//                     <3=> Three cycle less at the begining and the end of access
;//       <o1.24..26> RWSETUP: Read and Write Signal Setup Time <0-7>
;//       <o1.28..30> RWHOLD: Read and Write Signal Hold Time <0-7>
;//     </e>
SMC_CSR5_SETUP  EQU     0x00000000
SMC_CSR5_Val    EQU     0x00000000

;//     <e> Chip Select Register 6 (SMC_CSR6)
;//       <o1.0..6>   NWS: Number of Wait States <0-127>
;//       <o1.7>      WSEN: Wait State Enabled
;//       <o1.8..11>  TDF: Data Float Time <0-15>
;//       <o1.12>     BAT: Byte Access Type  
;//                     <0=> Chip Select line connected to  8-bit wide (2 or 4) devices
;//                     <1=> Chip Select line connected to 16-bit wide device
;//       <o1.13..14> DBW: Data Bus Width
;//                     <0=> Reserved     <1=> 16-bit
;//                     <2=> 8-bit        <3=> Reserved
;//       <o1.15>     DRP: Data Read Protocol
;//                     <0=> Standard Read Protocol is used
;//                     <1=> Early Read Protocol is used
;//       <o1.16..17> ACSS: Address to Chip Select Setup
;//                     <0=> Standard, asserted at the bigining of access and deasserted at the end
;//                     <1=> One cycle less at the begining and the end of access
;//                     <2=> Two cycle less at the begining and the end of access
;//                     <3=> Three cycle less at the begining and the end of access
;//       <o1.24..26> RWSETUP: Read and Write Signal Setup Time <0-7>
;//       <o1.28..30> RWHOLD: Read and Write Signal Hold Time <0-7>
;//     </e>
SMC_CSR6_SETUP  EQU     0x00000000
SMC_CSR6_Val    EQU     0x00000000

;//     <e> Chip Select Register 7 (SMC_CSR7)
;//       <o1.0..6>   NWS: Number of Wait States <0-127>
;//       <o1.7>      WSEN: Wait State Enabled
;//       <o1.8..11>  TDF: Data Float Time <0-15>
;//       <o1.12>     BAT: Byte Access Type  
;//                     <0=> Chip Select line connected to  8-bit wide (2 or 4) devices
;//                     <1=> Chip Select line connected to 16-bit wide device
;//       <o1.13..14> DBW: Data Bus Width
;//                     <0=> Reserved     <1=> 16-bit
;//                     <2=> 8-bit        <3=> Reserved
;//       <o1.15>     DRP: Data Read Protocol
;//                     <0=> Standard Read Protocol is used
;//                     <1=> Early Read Protocol is used
;//       <o1.16..17> ACSS: Address to Chip Select Setup
;//                     <0=> Standard, asserted at the bigining of access and deasserted at the end
;//                     <1=> One cycle less at the begining and the end of access
;//                     <2=> Two cycle less at the begining and the end of access
;//                     <3=> Three cycle less at the begining and the end of access
;//       <o1.24..26> RWSETUP: Read and Write Signal Setup Time <0-7>
;//       <o1.28..30> RWHOLD: Read and Write Signal Hold Time <0-7>
;//     </e>
;//   </h>
SMC_CSR7_SETUP  EQU     0x00000000
SMC_CSR7_Val    EQU     0x00000000

;//   <e> External Bus Interface Configuration
;//     <h> Chip Select Assignment Register (EBI_CSA)
;//       <o1.0>      CS0A: Chip Select 0 Assignment
;//                     <0=> Assigned to the Static Memory Controller
;//                     <1=> Assigned to the Burst Flash Controller
;//       <o1.1>      CS1A: Chip Select 1 Assignment
;//                     <0=> Assigned to the Static Memory Controller
;//                     <1=> Assigned to the SDRAM Controller
;//       <o1.3>      CS3A: Chip Select 3 Assignment
;//                     <0=> Assigned to the Static Memory Controller
;//                     <1=> Assigned to the SMC and NAND Flash/SmartMedia Logic activated
;//       <o1.4>      CS4A: Chip Select 4 Assignment
;//                     <0=> Assigned to the Static Memory Controller and NCS4, NCS5 and NCS6
;//                     <1=> Assigned to the SMC and Compact Flash Logic activated
;//     </h>
;//
;//     <h> Configuration Register (EBI_CFGR)
;//       <o2.0>      DBPUC: Data Bus Pull-Up Configuration
;//                     <0=> Internally pulled-up to the VDDIOM power supply
;//                     <1=> Not internally pulled-up
;//     </h>
;//   </e>
EBI_CFG_SETUP   EQU     0x00000001
EBI_CSA_Val     EQU     0x00000002
EBI_CFGR_Val    EQU     0x00000000

;//   <e> SDRAM Controller (SDRAMC)
SDRAMC_SETUP    EQU     1

;//     <h> Mode Register (SDRAMC_MR)
;//       <o0.0..3>   MODE: SDRAMC Command Mode
;//                     <i> 0 - Normal Mode, SDRAM is decoded normally
;//                     <i> 1 - SDRAM Controller issues NOP command on SDRAM access
;//                     <i> 2 - SDRAM Controller issues an "All Bank Precharge"
;//                     <i>     command when SDRAM is accessed
;//                     <i> 3 - SDRAM Controller issues an "Load Mode Register"
;//                     <i>     command when SDRAM is accessed
;//                     <i> 4 - SDRAM Controller issues an "Refresh", previously an 
;//                     <i>     "All Bank Precharge" command must be issued
;//                     <0=> Normal Mode          <1=> NOP Command
;//                     <2=> All Banks Precharge  <3=> Load Mode Register
;//                     <4=> Refresh
;//       <o0.4>      DBW: Data Bus Width
;//                     <0=> 32 bits              <1=> 16 bits
;//     </h>
SDRAMC_MR_Val   EQU     0x00000000

;//     <h> Refresh Timer Register (SDRAMC_TR)
;//       <o0.0..12>  COUNT: SDRAMC Refresh Timer Count <0-4095>
;//                     <i> This 12-bit field is loaded into a timer that generates
;//                     <i> the refresh pulse
;//     </h>
SDRAMC_TR_Val   EQU     0x000002E0

;//     <h> Configuration Register (SDRAMC_CR)
;//       <o0.0..1>   NC: Number of Column Bits
;//                     <0=> 8  <1=> 9  <2=> 10 <3=> 11
;//       <o0.2..3>   NR: Number of Row Bits
;//                     <0=> 11 <1=> 12 <2=> 13  <3=> Reserved
;//       <o0.4>      NB: Number of Banks
;//                     <0=> 2  <1=> 4
;//       <o0.5..6>   CAS: CAS Latency
;//                     <0=> Reserved <1=> Reserved <2=> 2  <3=> Reserved
;//       <o0.7..10>  TWR: Write Recovery Delay <2-15>
;//                     <i> Defines Write Recovery Time in cycles,
;//                     <i> if it is less than 2 cycles, 2 clock periods are inserted
;//       <o0.11..14> TRC: Row Cycle Delay <2-15>
;//                     <i> Defines delay between Refresh and an Activate 
;//                     <i> Command in cycles,
;//                     <i> if it is less than 2 cycles, 2 clock periods are used
;//       <o0.15..18> TRP: Row Precharge Delay <2-15>
;//                     <i> Defines delay between Precharge Command
;//                     <i> and another Command in cycles,
;//                     <i> if it is less than 2 cycles, 2 clock periods are used
;//       <o0.19..22> TRCD: Row to Column Delay <2-15>
;//                     <i> Defines delay between Activate Command
;//                     <i> and a Read/Write Command in cycles,
;//                     <i> if it is less than 2 cycles, 2 clock periods are used
;//       <o0.23..26> TRAS: Active to Precharge Delay <2-15>
;//                     <i> Defines delay between Activate Command
;//                     <i> and a Precharge Command in cycles,
;//                     <i> if it is less than 2 cycles, 2 clock periods are used
;//       <o0.27..30> TXSR: Exit Self Refresh to Active Delay <1-15>
;//                     <i> Defines delay between SCKE set high
;//                     <i> and an Activate Command in cycles, number of cycles
;//                     <i> is between 0.5 and 15.5, 0.5 is used for value 0 also
;//     </h>
SDRAMC_CR_Val   EQU     0x2188C155

;//     <h> Self-refresh Register (SDRAMC_SRR)
;//       <o0.0>      SRR: Self-refresh Enabled
;//     </h>
SDRAMC_SRR_Val  EQU     0x00001955

;//     <h> Interrupt Enable Register (SDRAMC_IER)
;//       <o0.0>      RES: Refresh Error interrupt Enabled
;//     </h>
SDRAMC_IER_Val  EQU     0x00000000

;//   </e>

;//   <e> Burst Flash Controller (BFC)
;//     <o1.0..1>     BFCOM: Burst Flash Controller Operating Mode
;//                     <0=> Disabled   <1=> Asynchronous 
;//                     <2=> Burst Read <3=> Reserved
;//     <o1.2..3>     BFCC: Burst Flash Controller Clock
;//                     <0=> Reserved         <1=> Master Clock 
;//                     <2=> Master Clock / 2 <3=> Master Clock / 4
;//     <o1.4..7>     AVL: Address Valid Latency <0-15>
;//                     <i> Is a number of BFC Clock Cycles from the first BFCK
;//                     <i> rising edge when BFAVD is asserted to the BFCK rising
;//                     <i> edge that samples read data
;//                     <i> The latency is equal to AVL + 1
;//     <o1.8..10>    PAGES: Page Size
;//                     <0=> No page handling <1=> 16 bytes page 
;//                     <2=> 32 bytes page    <3=> 64 bytes page 
;//                     <4=> 128 bytes page   <5=> 256 bytes page 
;//                     <6=> 512 bytes page   <7=> 1024 bytes page 
;//     <o1.12..13>   OEL: Output Enable Latency <1-3>
;//                     <i> Defines the number of idle cycles inserted after each 
;//                     <i> level change on the BFOE output enable signal
;//     <o1.16>       BAAEN: Burst Address Advance Enable
;//     <o1.17>       BFOEH: Burst Flash Output Enable Handling
;//     <o1.18>       MUXEN: Multiplexed Bus Enable
;//     <o1.19>       RDYEN: Ready Enable Mode
;//   </e>
BFC_SETUP       EQU     0
BFC_MR_Val      EQU     0x00000000

;// </e>


; Power Management Controller (PMC) definitions
PMC_BASE        EQU     0xFFFFFC00      ; PMC Base Address
PMC_SCER_OFS    EQU     0x00            ; Sys Clk Enable Reg      Address Offset
PMC_SCDR_OFS    EQU     0x04            ; Sys Clk Disable Reg     Address Offset
PMC_SCSR_OFS    EQU     0x08            ; Sys Clk Status Reg      Address Offset
PMC_PCER_OFS    EQU     0x10            ; Periph Clk Enable Reg   Address Offset
PMC_PCDR_OFS    EQU     0x14            ; Periph Clk Disable Reg  Address Offset
PMC_PCSR_OFS    EQU     0x18            ; Periph Clk Status Reg   Address Offset
CKGR_MOR_OFS    EQU     0x20            ; Main Oscillator Reg     Address Offset
CKGR_MCFR_OFS   EQU     0x24            ; Main Clock Freq Reg     Address Offset
CKGR_PLLAR_OFS  EQU     0x28            ; PLLA Reg                Address Offset
CKGR_PLLBR_OFS  EQU     0x2C            ; PLLA Reg                Address Offset
PMC_MCKR_OFS    EQU     0x30            ; Master Clock Reg        Address Offset
PMC_PCK0_OFS    EQU     0x40            ; Programmable Clk 0 Reg  Address Offset
PMC_PCK1_OFS    EQU     0x44            ; Programmable Clk 1 Reg  Address Offset
PMC_PCK2_OFS    EQU     0x48            ; Programmable Clk 2 Reg  Address Offset
PMC_PCK3_OFS    EQU     0x4C            ; Programmable Clk 3 Reg  Address Offset
PMC_IER_OFS     EQU     0x60            ; Interrupt Enable  Reg   Address Offset
PMC_IDR_OFS     EQU     0x64            ; Interrupt Disable Reg   Address Offset
PMC_SR_OFS      EQU     0x68            ; Status Reg              Address Offset
PMC_IMR_OFS     EQU     0x6C            ; Interrupt Mask Reg      Address Offset

; Bit constants
PMC_MOSCEN      EQU     (1<<0)          ; Main Oscillator Enable
PMC_MUL         EQU     (0x7FF<<16)     ; PLL Multiplier
PMC_MOSCS       EQU     (1<<0)          ; Main Oscillator Stable
PMC_LOCKA       EQU     (1<<1)          ; PLL A Lock Status
PMC_LOCKB       EQU     (1<<2)          ; PLL A Lock Status
PMC_MCKRDY      EQU     (1<<3)          ; Master Clock Status

;// <e> Power Management Controller (PMC)
;//   <h> System Clock Enable Register (PMC_SCER)
;//     <o1.0>      PCK: Processor Clock Enable
;//     <o1.1>      UDP: USB Device Port Clock Enable
;//     <o1.2>      MCKUDP: USB Device Port Master Clock Automatic Disable on Suspend Enable
;//     <o1.4>      UHP: USB Host Port Clock Enable
;//     <o1.8>      PCK0: Programmable Clock Output Enable
;//     <o1.9>      PCK1: Programmable Clock Output Enable
;//     <o1.10>     PCK2: Programmable Clock Output Enable
;//     <o1.11>     PCK3: Programmable Clock Output Enable