f00156b4287e001d1e6aa8d80b189b47

nios ii sopc关于ISP1362和DM9000A的工程

/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * d:\GX_CIDE_SOPC\EP3C80\projects\cide_7f\software\syslib\..\..\nios2_7f.ptf
 *
 * Generated: 2008-09-09 10:27:06.765
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "nios2_7f"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONEIII"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x015028a0
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x015028a0
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x015028a0
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 50000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "small"
#define NIOS2_BIG_ENDIAN 0

#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x00800020
#define NIOS2_RESET_ADDR 0x01200000
#define NIOS2_BREAK_ADDR 0x01501020

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SYSID
#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_TRI_STATE_BRIDGE
#define __ALTERA_AVALON_CFI_FLASH
#define __ALTERA_AVALON_CF
#define __GX_SRAM_256_16
#define __ALTERA_AVALON_MUTEX
#define __ALTERA_AVALON_TIMER
#define __GX_ISP1362

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x015028a0
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 0
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart

/*
 * sdram configuration
 *
 */

#define SDRAM_NAME "/dev/sdram"
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_BASE 0x00800000
#define SDRAM_SPAN 8388608
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SIM_MODEL_BASE 1
#define SDRAM_SDRAM_DATA_WIDTH 16
#define SDRAM_SDRAM_ADDR_WIDTH 12
#define SDRAM_SDRAM_ROW_WIDTH 12
#define SDRAM_SDRAM_COL_WIDTH 8
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_POWERUP_DELAY 100.0
#define SDRAM_CAS_LATENCY 3
#define SDRAM_T_RFC 70.0
#define SDRAM_T_RP 20.0
#define SDRAM_T_MRD 3
#define SDRAM_T_RCD 20.0
#define SDRAM_T_AC 5.5
#define SDRAM_T_WR 14.0
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_INIT_NOP_DELAY 0.0
#define SDRAM_SHARED_DATA 0
#define SDRAM_SDRAM_BANK_WIDTH 2
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_IS_INITIALIZED 1
#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller

/*
 * led_pio configuration
 *
 */

#define LED_PIO_NAME "/dev/led_pio"
#define LED_PIO_TYPE "altera_avalon_pio"
#define LED_PIO_BASE 0x01502860
#define LED_PIO_SPAN 16
#define LED_PIO_DO_TEST_BENCH_WIRING 0
#define LED_PIO_DRIVEN_SIM_VALUE 0
#define LED_PIO_HAS_TRI 0
#define LED_PIO_HAS_OUT 1
#define LED_PIO_HAS_IN 0
#define LED_PIO_CAPTURE 0
#define LED_PIO_DATA_WIDTH 8
#define LED_PIO_RESET_VALUE 0
#define LED_PIO_EDGE_TYPE "NONE"
#define LED_PIO_IRQ_TYPE "NONE"
#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define LED_PIO_FREQ 50000000
#define ALT_MODULE_CLASS_led_pio altera_avalon_pio

/*
 * sysid configuration
 *
 */

#define SYSID_NAME "/dev/sysid"
#define SYSID_TYPE "altera_avalon_sysid"
#define SYSID_BASE 0x01502890
#define SYSID_SPAN 8
#define SYSID_ID 291233203u
#define SYSID_TIMESTAMP 1220925038u
#define SYSID_REGENERATE_VALUES 0
#define ALT_MODULE_CLASS_sysid altera_avalon_sysid

/*
 * epcs_controller configuration
 *
 */

#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"
#define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"
#define EPCS_CONTROLLER_BASE 0x01501800
#define EPCS_CONTROLLER_SPAN 2048
#define EPCS_CONTROLLER_IRQ 1
#define EPCS_CONTROLLER_DATABITS 8
#define EPCS_CONTROLLER_TARGETCLOCK 20
#define EPCS_CONTROLLER_CLOCKUNITS "MHz"
#define EPCS_CONTROLLER_CLOCKMULT 1000000
#define EPCS_CONTROLLER_NUMSLAVES 1
#define EPCS_CONTROLLER_ISMASTER 1
#define EPCS_CONTROLLER_CLOCKPOLARITY 0
#define EPCS_CONTROLLER_CLOCKPHASE 0
#define EPCS_CONTROLLER_LSBFIRST 0
#define EPCS_CONTROLLER_EXTRADELAY 0
#define EPCS_CONTROLLER_TARGETSSDELAY 100
#define EPCS_CONTROLLER_DELAYUNITS "us"
#define EPCS_CONTROLLER_DELAYMULT "1e-006"
#define EPCS_CONTROLLER_PREFIX "epcs_"
#define EPCS_CONTROLLER_REGISTER_OFFSET 0x400
#define EPCS_CONTROLLER_USE_ASMI_ATOM 0
#define EPCS_CONTROLLER_CLOCKUNIT "kHz"
#define EPCS_CONTROLLER_DELAYUNIT "us"
#define ALT_MODULE_CLASS_epcs_controller altera_avalon_epcs_flash_controller

/*
 * message_buffer_ram configuration
 *
 */

#define MESSAGE_BUFFER_RAM_NAME "/dev/message_buffer_ram"
#define MESSAGE_BUFFER_RAM_TYPE "altera_avalon_onchip_memory2"
#define MESSAGE_BUFFER_RAM_BASE 0x01502000
#define MESSAGE_BUFFER_RAM_SPAN 2048
#define MESSAGE_BUFFER_RAM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define MESSAGE_BUFFER_RAM_RAM_BLOCK_TYPE "AUTO"
#define MESSAGE_BUFFER_RAM_INIT_CONTENTS_FILE "message_buffer_ram"
#define MESSAGE_BUFFER_RAM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define MESSAGE_BUFFER_RAM_GUI_RAM_BLOCK_TYPE "Automatic"
#define MESSAGE_BUFFER_RAM_WRITEABLE 1
#define MESSAGE_BUFFER_RAM_DUAL_PORT 0
#define MESSAGE_BUFFER_RAM_SIZE_VALUE 2048
#define MESSAGE_BUFFER_RAM_SIZE_MULTIPLE 1
#define MESSAGE_BUFFER_RAM_USE_SHALLOW_MEM_BLOCKS 0
#define MESSAGE_BUFFER_RAM_INIT_MEM_CONTENT 1
#define MESSAGE_BUFFER_RAM_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define MESSAGE_BUFFER_RAM_INSTANCE_ID "NONE"
#define MESSAGE_BUFFER_RAM_READ_DURING_WRITE_MODE "DONT_CARE"
#define MESSAGE_BUFFER_RAM_IGNORE_AUTO_BLOCK_TYPE_ASSIGNMENT 1
#define MESSAGE_BUFFER_RAM_CONTENTS_INFO ""
#define ALT_MODULE_CLASS_message_buffer_ram altera_avalon_onchip_memory2

/*
 * ext_bus configuration
 *
 */

#define EXT_BUS_NAME "/dev/ext_bus"
#define EXT_BUS_TYPE "altera_avalon_tri_state_bridge"
#define ALT_MODULE_CLASS_ext_bus altera_avalon_tri_state_bridge

/*
 * flash configuration
 *
 */

#define FLASH_NAME "/dev/flash"
#define FLASH_TYPE "altera_avalon_cfi_flash"
#define FLASH_BASE 0x01200000
#define FLASH_SPAN 2097152
#define FLASH_SETUP_VALUE 40
#define FLASH_WAIT_VALUE 160
#define FLASH_HOLD_VALUE 40
#define FLASH_TIMING_UNITS "ns"
#define FLASH_UNIT_MULTIPLIER 1
#define FLASH_SIZE 2097152
#define ALT_MODULE_CLASS_flash altera_avalon_cfi_flash

/*
 * cf/ctl configuration
 *
 */

#define CF_CTL_NAME "/dev/cf"
#define CF_CTL_TYPE "altera_avalon_cf"
#define CF_CTL_BASE 0x01502870
#define CF_CTL_SPAN 16
#define CF_CTL_IRQ 2
#define ALT_MODULE_CLASS_cf altera_avalon_cf

/*
 * cf/ide configuration
 *
 */

#define CF_IDE_NAME "/dev/cf"
#define CF_IDE_TYPE "altera_avalon_cf"
#define CF_IDE_BASE 0x01502800
#define CF_IDE_SPAN 64
#define CF_IDE_IRQ 3
#define ALT_MODULE_CLASS_cf altera_avalon_cf

/*
 * sram configuration
 *
 */

#define SRAM_NAME "/dev/sram"
#define SRAM_TYPE "gx_sram_256_16"
#define SRAM_BASE 0x01480000
#define SRAM_SPAN 524288
#define SRAM_TERMINATED_PORTS ""
#define ALT_MODULE_CLASS_sram gx_sram_256_16

/*
 * message_buffer_mutex configuration
 *
 */

#define MESSAGE_BUFFER_MUTEX_NAME "/dev/message_buffer_mutex"
#define MESSAGE_BUFFER_MUTEX_TYPE "altera_avalon_mutex"
#define MESSAGE_BUFFER_MUTEX_BASE 0x01502898
#define MESSAGE_BUFFER_MUTEX_SPAN 8
#define MESSAGE_BUFFER_MUTEX_VALUE_WIDTH 16
#define MESSAGE_BUFFER_MUTEX_OWNER_WIDTH 16
#define MESSAGE_BUFFER_MUTEX_VALUE_INIT 0
#define MESSAGE_BUFFER_MUTEX_OWNER_INIT 0
#define ALT_MODULE_CLASS_message_buffer_mutex altera_avalon_mutex

/*
 * high_res_timer configuration
 *
 */

#define HIGH_RES_TIMER_NAME "/dev/high_res_timer"
#define HIGH_RES_TIMER_TYPE "altera_avalon_timer"
#define HIGH_RES_TIMER_BASE 0x01502840
#define HIGH_RES_TIMER_SPAN 32
#define HIGH_RES_TIMER_IRQ 4
#define HIGH_RES_TIMER_ALWAYS_RUN 0
#define HIGH_RES_TIMER_FIXED_PERIOD 0
#define HIGH_RES_TIMER_SNAPSHOT 1
#define HIGH_RES_TIMER_PERIOD 1
#define HIGH_RES_TIMER_PERIOD_UNITS "ms"
#define HIGH_RES_TIMER_RESET_OUTPUT 0
#define HIGH_RES_TIMER_TIMEOUT_PULSE_OUTPUT 0
#define HIGH_RES_TIMER_LOAD_VALUE 49999
#define HIGH_RES_TIMER_COUNTER_SIZE 32
#define HIGH_RES_TIMER_MULT 0.0010
#define HIGH_RES_TIMER_TICKS_PER_SEC 1000
#define HIGH_RES_TIMER_FREQ 50000000
#define ALT_MODULE_CLASS_high_res_timer altera_avalon_timer

/*
 * isp1362/avalon_slave_0 configuration
 *
 */

#define ISP1362_AVALON_SLAVE_0_NAME "/dev/isp1362"
#define ISP1362_AVALON_SLAVE_0_TYPE "gx_isp1362"
#define ISP1362_AVALON_SLAVE_0_BASE 0x01502880
#define ISP1362_AVALON_SLAVE_0_SPAN 16
#define ISP1362_AVALON_SLAVE_0_IRQ 5
#define ISP1362_AVALON_SLAVE_0_TERMINATED_PORTS ""
#define ALT_MODULE_CLASS_isp1362 gx_isp1362

/*
 * isp1362/avalon_slave_1 configuration
 *
 */

#define ISP1362_AVALON_SLAVE_1_NAME "/dev/isp1362"
#define ISP1362_AVALON_SLAVE_1_TYPE "gx_isp1362"
#define ISP1362_AVALON_SLAVE_1_BASE 0x015028a8
#define ISP1362_AVALON_SLAVE_1_SPAN 4
#define ISP1362_AVALON_SLAVE_1_IRQ 6
#define ISP1362_AVALON_SLAVE_1_TERMINATED_PORTS ""
#define ALT_MODULE_CLASS_isp1362 gx_isp1362

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK HIGH_RES_TIMER
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM
#define ALT_RODATA_DEVICE     SDRAM
#define ALT_RWDATA_DEVICE     SDRAM
#define ALT_EXCEPTIONS_DEVICE SDRAM
#define ALT_RESET_DEVICE      FLASH


#endif /* __SYSTEM_H_ */