generated_app.mk

nios ii sopc关于ISP1362和DM9000A的工程

# generated_app.mk
#
# Machine generated for a CPU named "cpu" as defined in:
# d:\GX_CIDE_SOPC\EP2C20_dep\cide_7f\software\syslib\..\..\nios2_7f.ptf
#
# Generated: 2008-12-03 13:19:09.109

# DO NOT MODIFY THIS FILE
#
#   Changing this file will have subtle consequences
#   which will almost certainly lead to a nonfunctioning
#   system. If you do modify this file, be aware that your
#   changes will be overwritten and lost when this file
#   is generated again.
#
# DO NOT MODIFY THIS FILE

# assuming the Quartus project directory is the same as the PTF directory
QUARTUS_PROJECT_DIR = D:/GX_CIDE_SOPC/EP2C20_dep/cide_7f

# the simulation directory is a subdirectory of the PTF directory
SIMDIR = $(QUARTUS_PROJECT_DIR)/nios2_7f_sim

DBL_QUOTE := "


# macros defined by/for epcs_controller & flash1
EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX = $(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1:0=)
EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1 = $(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)
BOOTS_FROM_EPCS = 0
BOOT_COPIER_EPCS = boot_loader_epcs.srec
CPU_CLASS = altera_nios2
CPU_RESET_ADDRESS = 0x0
FLASH1_FLASHTARGET_ALT_SIM_PREFIX = $(FLASH1_FLASHTARGET_TMP1:0=)
FLASH1_FLASHTARGET_TMP1 = $(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)
BOOT_COPIER = boot_loader_cfi.srec


all: delete_placeholder_warning sim flashfiles hex

delete_placeholder_warning: do_delete_placeholder_warning
.PHONY: delete_placeholder_warning

sim: $(SIMDIR)/dummy_file
.PHONY: sim

flashfiles: $(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash $(FLASH1_FLASHTARGET_ALT_SIM_PREFIX)flash1.flash
.PHONY: flashfiles

hex: $(QUARTUS_PROJECT_DIR)/onchip_ram.hex
.PHONY: hex

verifysysid: dummy_verifysysid_file
.PHONY: verifysysid

do_delete_placeholder_warning:
	rm -f $(SIMDIR)/contents_file_warning.txt
.PHONY: do_delete_placeholder_warning

$(SIMDIR)/dummy_file: $(ELF)
	if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi
	@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \(Note: This does not affect the instruction set simulator.\)
	touch $(SIMDIR)/dummy_file

$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash: $(ELF)
	@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then echo Post-processing to create $(notdir $@) ; elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER_EPCS)$(DBL_QUOTE) --outfile=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --epcs --base=0x0 --end=0x7FFFFFFF  ; fi

$(FLASH1_FLASHTARGET_ALT_SIM_PREFIX)flash1.flash: $(ELF)
	@echo Post-processing to create $(notdir $@)
	elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(FLASH1_FLASHTARGET_ALT_SIM_PREFIX)flash1.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x3FFFFF --reset=$(CPU_RESET_ADDRESS)

$(QUARTUS_PROJECT_DIR)/onchip_ram.hex: $(ELF)
	@echo Post-processing to create $(notdir $@)
	elf2hex $(ELF) 0x00502000 0x5027FF --width=16 $(QUARTUS_PROJECT_DIR)/onchip_ram.hex --create-lanes=0

dummy_verifysysid_file:
	nios2-download $(JTAG_CABLE)                                --sidp=0x00502898 --id=992816754 --timestamp=1226459892
.PHONY: dummy_verifysysid_file


generated_app_clean:
	$(RM) $(SIMDIR)/dummy_file
	$(RM) $(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash
	$(RM) $(FLASH1_FLASHTARGET_ALT_SIM_PREFIX)flash1.flash
	$(RM) $(QUARTUS_PROJECT_DIR)/onchip_ram.hex
.PHONY: generated_app_clean