📄 spwm_am_sin_tab.lst
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< .DEFINE CW_TMR1_TGAIE_Enable 0x0001
< .DEFINE CW_TMR1_TGBIE_Enable (0x0001 << 1)
< .DEFINE CW_TMR1_TGCIE_Enable (0x0001 << 2)
< .DEFINE CW_TMR1_TPRIE_Enable (0x0001 << 4)
< .DEFINE CW_TMR1_TCVIE_Enable (0x0001 << 5)
< .DEFINE CW_TMR1_TCUIE_Enable (0x0001 << 6)
< .DEFINE CW_TMR1_TADSE_Enable (0x0001 << 7)
< .DEFINE CW_TMR1_PDCIE_Enable (0x0001 << 8)
<
<
< // P_TMR2_INT register //
< // word set //
< .DEFINE CW_TMR2_TGAIE_Enable 0x0001
< .DEFINE CW_TMR2_TGBIE_Enable (0x0001 << 1)
< .DEFINE CW_TMR2_TPRIE_Enable (0x0001 << 4)
< .DEFINE CW_TMR2_TADSE_Enable (0x0001 << 7)
<
<
< // P_TMR3_INT register //
< // word set //
< .DEFINE CW_TMR3_TGDIE_Enable (0x0001 << 3)
< .DEFINE CW_TMR3_TPRIE_Enable (0x0001 << 4)
< .DEFINE CW_TMR3_TADSE_Enable (0x0001 << 7)
<
<
< // P_TMR4_INT register //
< // word set //
< .DEFINE CW_TMR4_TGDIE_Enable (0x0001 << 3)
< .DEFINE CW_TMR4_TPRIE_Enable (0x0001 << 4)
< .DEFINE CW_TMR4_TADSE_Enable (0x0001 << 7)
<
<
< // P_TMR0_Status register //
< // word set //
< .DEFINE CW_TMR0_TGAIF_Enable 0x0001
< .DEFINE CW_TMR0_TGBIF_Enable (0x0001 << 1)
< .DEFINE CW_TMR0_TGCIF_Enable (0x0001 << 2)
< .DEFINE CW_TMR0_TPRIF_Enable (0x0001 << 4)
< .DEFINE CW_TMR0_TCVIF_Enable (0x0001 << 5)
< .DEFINE CW_TMR0_TCUIF_Enable (0x0001 << 6)
< .DEFINE CW_TMR0_TCDF_Enable (0x0001 << 7)
< .DEFINE CW_TMR0_PDCIF_Enable (0x0001 << 8)
<
<
< // P_TMR1_Status register //
< // word set //
< .DEFINE CW_TMR1_TGAIF_Enable 0x0001
< .DEFINE CW_TMR1_TGBIF_Enable (0x0001 << 1)
< .DEFINE CW_TMR1_TGCIF_Enable (0x0001 << 2)
< .DEFINE CW_TMR1_TPRIF_Enable (0x0001 << 4)
< .DEFINE CW_TMR1_TCVIF_Enable (0x0001 << 5)
< .DEFINE CW_TMR1_TCUIF_Enable (0x0001 << 6)
< .DEFINE CW_TMR1_TCDF_Enable (0x0001 << 7)
< .DEFINE CW_TMR1_PDCIF_Enable (0x0001 << 8)
<
<
< // P_TMR2_Status register //
< // word set //
< .DEFINE CW_TMR2_TGAIF_Enable 0x0001
< .DEFINE CW_TMR2_TGBIF_Enable (0x0001 << 1)
< .DEFINE CW_TMR2_TPRIF_Enable (0x0001 << 4)
< .DEFINE CW_TMR2_TCDF_Enable (0x0001 << 7)
<
<
< // P_TMR3_Status register //
< // word set //
< .DEFINE CW_TMR3_TGDIF_Enable (0x0001 << 3)
< .DEFINE CW_TMR3_TPRIF_Enable (0x0001 << 4)
< .DEFINE CW_TMR3_TCDF_Enable (0x0001 << 7)
<
<
< // P_TMR4_Status register //
< // word set //
< .DEFINE CW_TMR4_TGDIF_Enable (0x0001 << 3)
< .DEFINE CW_TMR4_TPRIF_Enable (0x0001 << 4)
< .DEFINE CW_TMR4_TCDF_Enable (0x0001 << 7)
<
<
< // P_TMR_Start register //
< // word set //
< .DEFINE CW_TMR_TMR0ST_Start 0x0001
< .DEFINE CW_TMR_TMR1ST_Start (0x0001 << 1)
< .DEFINE CW_TMR_TMR2ST_Start (0x0001 << 2)
< .DEFINE CW_TMR_TMR3ST_Start (0x0001 << 3)
< .DEFINE CW_TMR_TMR4ST_Start (0x0001 << 4)
<
<
< // P_TMR_Output register //
< // word set //
< .DEFINE CW_TMR_TMR3AOE_Enable 0x0001
< .DEFINE CW_TMR_TMR3BOE_Enable (0x0001 << 1)
< .DEFINE CW_TMR_TMR3COE_Enable (0x0001 << 2)
< .DEFINE CW_TMR_TMR3DOE_Enable (0x0001 << 3)
< .DEFINE CW_TMR_TMR3EOE_Enable (0x0001 << 4)
< .DEFINE CW_TMR_TMR3FOE_Enable (0x0001 << 5)
< .DEFINE CW_TMR_TMR4AOE_Enable (0x0001 << 8)
< .DEFINE CW_TMR_TMR4BOE_Enable (0x0001 << 9)
< .DEFINE CW_TMR_TMR4COE_Enable (0x0001 << 10)
< .DEFINE CW_TMR_TMR4DOE_Enable (0x0001 << 11)
< .DEFINE CW_TMR_TMR4EOE_Enable (0x0001 << 12)
< .DEFINE CW_TMR_TMR4FOE_Enable (0x0001 << 13)
<
<
< // P_TMR3_OutputCtrl register //
< // word set //
< .DEFINE CW_TMR3_UOC_Mode0 0x0000
< .DEFINE CW_TMR3_UOC_Mode1 0x0001
< .DEFINE CW_TMR3_UOC_Mode2 0x0002
< .DEFINE CW_TMR3_UOC_Mode3 0x0003
<
< .DEFINE CW_TMR3_VOC_Mode0 (0x0000 << 2)
< .DEFINE CW_TMR3_VOC_Mode1 (0x0001 << 2)
< .DEFINE CW_TMR3_VOC_Mode2 (0x0002 << 2)
< .DEFINE CW_TMR3_VOC_Mode3 (0x0003 << 2)
<
< .DEFINE CW_TMR3_WOC_Mode0 (0x0000 << 4)
< .DEFINE CW_TMR3_WOC_Mode1 (0x0001 << 4)
< .DEFINE CW_TMR3_WOC_Mode2 (0x0002 << 4)
< .DEFINE CW_TMR3_WOC_Mode3 (0x0003 << 4)
<
< .DEFINE CW_TMR3_SYNC_NoSync (0x0000 << 6)
< .DEFINE CW_TMR3_SYNC_PDR (0x0001 << 6)
< .DEFINE CW_TMR3_SYNC_TGB (0x0002 << 6)
< .DEFINE CW_TMR3_SYNC_TGC (0x0003 << 6)
<
< .DEFINE CW_TMR3_UPWM_Out_HL (0x0000 << 8)
< .DEFINE CW_TMR3_UPWM_Out_PWM (0x0001 << 8)
< .DEFINE CW_TMR3_VPWM_Out_HL (0x0000 << 9)
< .DEFINE CW_TMR3_VPWM_Out_PWM (0x0001 << 9)
< .DEFINE CW_TMR3_WPWM_Out_HL (0x0000 << 10)
< .DEFINE CW_TMR3_WPWM_Out_PWM (0x0001 << 10)
<
< .DEFINE CW_TMR3_POLP_Active_Low (0x0000 << 14)
< .DEFINE CW_TMR3_POLP_Active_High (0x0001 << 14)
<
< .DEFINE CW_TMR3_DUTYMODE_UCom (0x0000 << 15)
< .DEFINE CW_TMR3_DUTYMODE_Independent (0x0001 << 15)
<
< // POLP = 1 //
< .DEFINE CW_TMR3_POLP_1_UP_CPWM_UN_PWM (CW_TMR3_UOC_Mode0 | CW_TMR3_UPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_1_UP_L_UN_PWM (CW_TMR3_UOC_Mode1 | CW_TMR3_UPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_1_UP_PWM_UN_L (CW_TMR3_UOC_Mode2 | CW_TMR3_UPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_1_UP_PWM_UN_CPWM (CW_TMR3_UOC_Mode3 | CW_TMR3_UPWM_Out_PWM)
<
< .DEFINE CW_TMR3_POLP_1_VP_CPWM_VN_PWM (CW_TMR3_VOC_Mode0 | CW_TMR3_VPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_1_VP_L_VN_PWM (CW_TMR3_VOC_Mode1 | CW_TMR3_VPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_1_VP_PWM_VN_L (CW_TMR3_VOC_Mode2 | CW_TMR3_VPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_1_VP_PWM_VN_CPWM (CW_TMR3_VOC_Mode3 | CW_TMR3_VPWM_Out_PWM)
<
< .DEFINE CW_TMR3_POLP_1_WP_CPWM_WN_PWM (CW_TMR3_WOC_Mode0 | CW_TMR3_WPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_1_WP_L_WN_PWM (CW_TMR3_WOC_Mode1 | CW_TMR3_WPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_1_WP_PWM_WN_L (CW_TMR3_WOC_Mode2 | CW_TMR3_WPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_1_WP_PWM_WN_CPWM (CW_TMR3_WOC_Mode3 | CW_TMR3_WPWM_Out_PWM)
<
< .DEFINE CW_TMR3_POLP_1_UP_L_UN_L (CW_TMR3_UOC_Mode0 | CW_TMR3_UPWM_Out_HL)
< .DEFINE CW_TMR3_POLP_1_UP_L_UN_H (CW_TMR3_UOC_Mode1 | CW_TMR3_UPWM_Out_HL)
< .DEFINE CW_TMR3_POLP_1_UP_H_UN_L (CW_TMR3_UOC_Mode2 | CW_TMR3_UPWM_Out_HL)
< .DEFINE CW_TMR3_POLP_1_UP_H_UN_H (CW_TMR3_UOC_Mode3 | CW_TMR3_UPWM_Out_HL)
<
< .DEFINE CW_TMR3_POLP_1_VP_L_VN_L (CW_TMR3_VOC_Mode0 | CW_TMR3_VPWM_Out_HL)
< .DEFINE CW_TMR3_POLP_1_VP_L_VN_H (CW_TMR3_VOC_Mode1 | CW_TMR3_VPWM_Out_HL)
< .DEFINE CW_TMR3_POLP_1_VP_H_VN_L (CW_TMR3_VOC_Mode2 | CW_TMR3_VPWM_Out_HL)
< .DEFINE CW_TMR3_POLP_1_VP_H_VN_H (CW_TMR3_VOC_Mode3 | CW_TMR3_VPWM_Out_HL)
<
< .DEFINE CW_TMR3_POLP_1_WP_L_WN_L (CW_TMR3_WOC_Mode0 | CW_TMR3_WPWM_Out_HL)
< .DEFINE CW_TMR3_POLP_1_WP_L_WN_H (CW_TMR3_WOC_Mode1 | CW_TMR3_WPWM_Out_HL)
< .DEFINE CW_TMR3_POLP_1_WP_H_WN_L (CW_TMR3_WOC_Mode2 | CW_TMR3_WPWM_Out_HL)
< .DEFINE CW_TMR3_POLP_1_WP_H_WN_H (CW_TMR3_WOC_Mode3 | CW_TMR3_WPWM_Out_HL)
<
< // POLP = 0 //
< .DEFINE CW_TMR3_POLP_0_UP_PWM_UN_CPWM (CW_TMR3_UOC_Mode0 | CW_TMR3_UPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_0_UP_H_UN_CPWM (CW_TMR3_UOC_Mode1 | CW_TMR3_UPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_0_UP_CPWM_UN_H (CW_TMR3_UOC_Mode2 | CW_TMR3_UPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_0_UP_CPWM_UN_PWM (CW_TMR3_UOC_Mode3 | CW_TMR3_UPWM_Out_PWM)
<
< .DEFINE CW_TMR3_POLP_0_VP_PWM_VN_CPWM (CW_TMR3_VOC_Mode0 | CW_TMR3_VPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_0_VP_H_VN_CPWM (CW_TMR3_VOC_Mode1 | CW_TMR3_VPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_0_VP_CPWM_VN_H (CW_TMR3_VOC_Mode2 | CW_TMR3_VPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_0_VP_CPWM_VN_PWM (CW_TMR3_VOC_Mode3 | CW_TMR3_VPWM_Out_PWM)
<
< .DEFINE CW_TMR3_POLP_0_WP_PWM_WN_CPWM (CW_TMR3_WOC_Mode0 | CW_TMR3_WPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_0_WP_H_WN_CPWM (CW_TMR3_WOC_Mode1 | CW_TMR3_WPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_0_WP_CPWM_WN_H (CW_TMR3_WOC_Mode2 | CW_TMR3_WPWM_Out_PWM)
< .DEFINE CW_TMR3_POLP_0_WP_CPWM_WN_PWM (CW_TMR3_WOC_Mode3 | CW_TMR3_WPWM_Out_PWM)
<
< .DEFINE CW_TMR3_POLP_0_UP_H_UN_H (CW_TMR3_UOC_Mode0 | CW_TMR3_UPWM_Out_HL)
< .DEFINE CW_TMR3_POLP_0_UP_H_UN_L (CW_TMR3_UOC_Mode1 | CW_TMR3_UPWM_Out_HL)
< .DEFINE CW_TMR3_POLP_0_UP_L_UN_H (CW_TMR3_UOC_Mode2 | CW_TMR3_UPWM_Out_HL)
< .DEFINE CW_TMR3_POLP_0_UP_L_UN_L (CW_TMR3_UOC⌨️ 快捷键说明
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