📄 spwm_am_sin_tab.lst
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< .DEFINE CW_TMR3_CKEGS_Rising (0x0000 << 3)
< .DEFINE CW_TMR3_CKEGS_Falling (0x0001 << 3)
< .DEFINE CW_TMR3_CKEGS_Both (0x0002 << 3)
<
< .DEFINE CW_TMR3_CCLS_Disabled (0x0000 << 5)
< .DEFINE CW_TMR3_CCLS_PTR (0x0007 << 5)
<
< //.DEFINE CW_TMR3_LDOK (0x0001 << 9)
<
< .DEFINE CW_TMR3_MODE_Normal (0x0000 << 10)
< .DEFINE CW_TMR3_MODE_PWM_Edge (0x0008 << 10)
< .DEFINE CW_TMR3_MODE_PWM_Center (0x000A << 10)
<
< .DEFINE CW_TMR3_PRDINT_Period (0x0000 << 14)
< .DEFINE CW_TMR3_PRDINT_2Period (0x0001 << 14)
< .DEFINE CW_TMR3_PRDINT_4Period (0x0002 << 14)
< .DEFINE CW_TMR3_PRDINT_8Period (0x0003 << 14)
<
< // P_TMR4_Ctrl register //
< // word set //
< .DEFINE CW_TMR4_TMRPS_FCKdiv1 0x0000
< .DEFINE CW_TMR4_TMRPS_FCKdiv4 0x0001
< .DEFINE CW_TMR4_TMRPS_FCKdiv16 0x0002
< .DEFINE CW_TMR4_TMRPS_FCKdiv64 0x0003
< .DEFINE CW_TMR4_TMRPS_FCKdiv256 0x0004
< .DEFINE CW_TMR4_TMRPS_FCKdiv1024 0x0005
< .DEFINE CW_TMR4_TMRPS_TCLKA 0x0006
< .DEFINE CW_TMR4_TMRPS_TCLKB 0x0007
<
< .DEFINE CW_TMR4_CKEGS_Rising (0x0000 << 3)
< .DEFINE CW_TMR4_CKEGS_Falling (0x0001 << 3)
< .DEFINE CW_TMR4_CKEGS_Both (0x0002 << 3)
<
< .DEFINE CW_TMR4_CCLS_Disabled (0x0000 << 5)
< .DEFINE CW_TMR4_CCLS_PTR (0x0007 << 5)
<
< //.DEFINE CW_TMR4_LDOK (0x0001 << 9)
<
< .DEFINE CW_TMR4_MODE_Normal (0x0000 << 10)
< .DEFINE CW_TMR4_MODE_PWM_Edge (0x0008 << 10)
< .DEFINE CW_TMR4_MODE_PWM_Center (0x000A << 10)
<
< .DEFINE CW_TMR4_PRDINT_Period (0x0000 << 14)
< .DEFINE CW_TMR4_PRDINT_2Period (0x0001 << 14)
< .DEFINE CW_TMR4_PRDINT_4Period (0x0002 << 14)
< .DEFINE CW_TMR4_PRDINT_8Period (0x0003 << 14)
<
< // P_TMR0_IOCtrl register //
< // word set //
< .DEFINE CW_TMR0_IOAMOD_Output_00 0x0000
< .DEFINE CW_TMR0_IOAMOD_Output_01 0x0001
< .DEFINE CW_TMR0_IOAMOD_Output_10 0x0002
< .DEFINE CW_TMR0_IOAMOD_Output_11 0x0003
< .DEFINE CW_TMR0_IOAMOD_Output_Hold 0x0004
< .DEFINE CW_TMR0_IOAMOD_Capture_Rising 0x0008
< .DEFINE CW_TMR0_IOAMOD_Capture_Falling 0x0009
< .DEFINE CW_TMR0_IOAMOD_Capture_Both 0x000A
< .DEFINE CW_TMR0_IOAMOD_Capture_PDR 0x000C
<
< .DEFINE CW_TMR0_IOBMOD_Output_00 (0x0000 << 4)
< .DEFINE CW_TMR0_IOBMOD_Output_01 (0x0001 << 4)
< .DEFINE CW_TMR0_IOBMOD_Output_10 (0x0002 << 4)
< .DEFINE CW_TMR0_IOBMOD_Output_11 (0x0003 << 4)
< .DEFINE CW_TMR0_IOBMOD_Output_Hold (0x0004 << 4)
< .DEFINE CW_TMR0_IOBMOD_Capture_Rising (0x0008 << 4)
< .DEFINE CW_TMR0_IOBMOD_Capture_Falling (0x0009 << 4)
< .DEFINE CW_TMR0_IOBMOD_Capture_Both (0x000A << 4)
< .DEFINE CW_TMR0_IOBMOD_Capture_PDR (0x000C << 4)
<
< .DEFINE CW_TMR0_IOCMOD_Output_00 (0x0000 << 8)
< .DEFINE CW_TMR0_IOCMOD_Output_01 (0x0001 << 8)
< .DEFINE CW_TMR0_IOCMOD_Output_10 (0x0002 << 8)
< .DEFINE CW_TMR0_IOCMOD_Output_11 (0x0003 << 8)
< .DEFINE CW_TMR0_IOCMOD_Output_Hold (0x0004 << 8)
< .DEFINE CW_TMR0_IOCMOD_Capture_Rising (0x0008 << 8)
< .DEFINE CW_TMR0_IOCMOD_Capture_Falling (0x0009 << 8)
< .DEFINE CW_TMR0_IOCMOD_Capture_Both (0x000A << 8)
< .DEFINE CW_TMR0_IOCMOD_Capture_PDR (0x000C << 8)
<
<
< // P_TMR1_IOCtrl register //
< // word set //
< .DEFINE CW_TMR1_IOAMOD_Output_00 0x0000
< .DEFINE CW_TMR1_IOAMOD_Output_01 0x0001
< .DEFINE CW_TMR1_IOAMOD_Output_10 0x0002
< .DEFINE CW_TMR1_IOAMOD_Output_11 0x0003
< .DEFINE CW_TMR1_IOAMOD_Output_Hold 0x0004
< .DEFINE CW_TMR1_IOAMOD_Capture_Rising 0x0008
< .DEFINE CW_TMR1_IOAMOD_Capture_Falling 0x0009
< .DEFINE CW_TMR1_IOAMOD_Capture_Both 0x000A
< .DEFINE CW_TMR1_IOAMOD_Capture_PDR 0x000C
<
< .DEFINE CW_TMR1_IOBMOD_Output_00 (0x0000 << 4)
< .DEFINE CW_TMR1_IOBMOD_Output_01 (0x0001 << 4)
< .DEFINE CW_TMR1_IOBMOD_Output_10 (0x0002 << 4)
< .DEFINE CW_TMR1_IOBMOD_Output_11 (0x0003 << 4)
< .DEFINE CW_TMR1_IOBMOD_Output_Hold (0x0004 << 4)
< .DEFINE CW_TMR1_IOBMOD_Capture_Rising (0x0008 << 4)
< .DEFINE CW_TMR1_IOBMOD_Capture_Falling (0x0009 << 4)
< .DEFINE CW_TMR1_IOBMOD_Capture_Both (0x000A << 4)
< .DEFINE CW_TMR1_IOBMOD_Capture_PDR (0x000C << 4)
<
< .DEFINE CW_TMR1_IOCMOD_Output_00 (0x0000 << 8)
< .DEFINE CW_TMR1_IOCMOD_Output_01 (0x0001 << 8)
< .DEFINE CW_TMR1_IOCMOD_Output_10 (0x0002 << 8)
< .DEFINE CW_TMR1_IOCMOD_Output_11 (0x0003 << 8)
< .DEFINE CW_TMR1_IOCMOD_Output_Hold (0x0004 << 8)
< .DEFINE CW_TMR1_IOCMOD_Capture_Rising (0x0008 << 8)
< .DEFINE CW_TMR1_IOCMOD_Capture_Falling (0x0009 << 8)
< .DEFINE CW_TMR1_IOCMOD_Capture_Both (0x000A << 8)
< .DEFINE CW_TMR1_IOCMOD_Capture_PDR (0x000C << 8)
<
<
< // P_TMR2_IOCtrl register //
< // word set //
< .DEFINE CW_TMR2_IOAMOD_Output_00 0x0000
< .DEFINE CW_TMR2_IOAMOD_Output_01 0x0001
< .DEFINE CW_TMR2_IOAMOD_Output_10 0x0002
< .DEFINE CW_TMR2_IOAMOD_Output_11 0x0003
< .DEFINE CW_TMR2_IOAMOD_Output_Hold 0x0004
< .DEFINE CW_TMR2_IOAMOD_Capture_Rising 0x0008
< .DEFINE CW_TMR2_IOAMOD_Capture_Falling 0x0009
< .DEFINE CW_TMR2_IOAMOD_Capture_Both 0x000A
<
< .DEFINE CW_TMR2_IOBMOD_Output_00 (0x0000 << 4)
< .DEFINE CW_TMR2_IOBMOD_Output_01 (0x0001 << 4)
< .DEFINE CW_TMR2_IOBMOD_Output_10 (0x0002 << 4)
< .DEFINE CW_TMR2_IOBMOD_Output_11 (0x0003 << 4)
< .DEFINE CW_TMR2_IOBMOD_Output_Hold (0x0004 << 4)
< .DEFINE CW_TMR2_IOBMOD_Capture_Rising (0x0008 << 4)
< .DEFINE CW_TMR2_IOBMOD_Capture_Falling (0x0009 << 4)
< .DEFINE CW_TMR2_IOBMOD_Capture_Both (0x000A << 4)
<
<
< // P_TMR3_IOCtrl register //
< // word set //
< .DEFINE CW_TMR3_IOAMOD_Output_00 0x0000
< .DEFINE CW_TMR3_IOAMOD_Output_01 0x0001
< .DEFINE CW_TMR3_IOAMOD_Output_10 0x0002
< .DEFINE CW_TMR3_IOAMOD_Output_11 0x0003
< .DEFINE CW_TMR3_IOAMOD_Output_Hold 0x0004
<
< .DEFINE CW_TMR3_IOBMOD_Output_00 (0x0000 << 4)
< .DEFINE CW_TMR3_IOBMOD_Output_01 (0x0001 << 4)
< .DEFINE CW_TMR3_IOBMOD_Output_10 (0x0002 << 4)
< .DEFINE CW_TMR3_IOBMOD_Output_11 (0x0003 << 4)
< .DEFINE CW_TMR3_IOBMOD_Output_Hold (0x0004 << 4)
<
< .DEFINE CW_TMR3_IOCMOD_Output_00 (0x0000 << 8)
< .DEFINE CW_TMR3_IOCMOD_Output_01 (0x0001 << 8)
< .DEFINE CW_TMR3_IOCMOD_Output_10 (0x0002 << 8)
< .DEFINE CW_TMR3_IOCMOD_Output_11 (0x0003 << 8)
< .DEFINE CW_TMR3_IOCMOD_Output_Hold (0x0004 << 8)
<
<
< // P_TMR4_IOCtrl register //
< // word set //
< .DEFINE CW_TMR4_IOAMOD_Output_00 0x0000
< .DEFINE CW_TMR4_IOAMOD_Output_01 0x0001
< .DEFINE CW_TMR4_IOAMOD_Output_10 0x0002
< .DEFINE CW_TMR4_IOAMOD_Output_11 0x0003
< .DEFINE CW_TMR4_IOAMOD_Output_Hold 0x0004
<
< .DEFINE CW_TMR4_IOBMOD_Output_00 (0x0000 << 4)
< .DEFINE CW_TMR4_IOBMOD_Output_01 (0x0001 << 4)
< .DEFINE CW_TMR4_IOBMOD_Output_10 (0x0002 << 4)
< .DEFINE CW_TMR4_IOBMOD_Output_11 (0x0003 << 4)
< .DEFINE CW_TMR4_IOBMOD_Output_Hold (0x0004 << 4)
<
< .DEFINE CW_TMR4_IOCMOD_Output_00 (0x0000 << 8)
< .DEFINE CW_TMR4_IOCMOD_Output_01 (0x0001 << 8)
< .DEFINE CW_TMR4_IOCMOD_Output_10 (0x0002 << 8)
< .DEFINE CW_TMR4_IOCMOD_Output_11 (0x0003 << 8)
< .DEFINE CW_TMR4_IOCMOD_Output_Hold (0x0004 << 8)
<
<
< // P_TMR0_INT register //
< // word set //
< .DEFINE CW_TMR0_TGAIE_Enable 0x0001
< .DEFINE CW_TMR0_TGBIE_Enable (0x0001 << 1)
< .DEFINE CW_TMR0_TGCIE_Enable (0x0001 << 2)
< .DEFINE CW_TMR0_TPRIE_Enable (0x0001 << 4)
< .DEFINE CW_TMR0_TCVIE_Enable (0x0001 << 5)
< .DEFINE CW_TMR0_TCUIE_Enable (0x0001 << 6)
< .DEFINE CW_TMR0_TADSE_Enable (0x0001 << 7)
< .DEFINE CW_TMR0_PDCIE_Enable (0x0001 << 8)
<
<
< // P_TMR1_INT register //
< // word set //
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