📄 spwm_am_sin_tab.lst
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< .DEFINE P_Fault1_Release_ADDR 0x746A
< .DEFINE P_Fault2_Release_ADDR 0x746B
<
< //***************************************************************************//
< //***************************************************************************//
< // D. 10-bit ADC converter register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_ADC_Setup_ADDR 0x7160
< .DEFINE P_ADC_Ctrl_ADDR 0x7161
< .DEFINE P_ADC_Data_ADDR 0x7162
< .DEFINE P_ADC_Channel_ADDR 0x7166
<
< //***************************************************************************//
< //***************************************************************************//
< // E. Standard Peripheral Interface SPI register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_SPI_Ctrl_ADDR 0x7140
< .DEFINE P_SPI_TxStatus_ADDR 0x7141
< .DEFINE P_SPI_TxBuf_ADDR 0x7142
< .DEFINE P_SPI_RxStatus_ADDR 0x7143
< .DEFINE P_SPI_RxBuf_ADDR 0x7144
<
< //***************************************************************************//
< //***************************************************************************//
< // F. Flash organization and control register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_Flash_RW_ADDR 0x7554
< .DEFINE P_Flash_Ctrl_ADDR 0x7555
<
< //***************************************************************************//
< //***************************************************************************//
< // G. UART Control Register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_UART_Data_ADDR 0x7100
< .DEFINE P_UART_RXStatus_ADDR 0x7101
< .DEFINE P_UART_Ctrl_ADDR 0x7102
< .DEFINE P_UART_BaudRate_ADDR 0x7103
< .DEFINE P_UART_Status_ADDR 0x7104
<
< //***************************************************************************//
< //***************************************************************************//
< // H. Compare Match Timer Register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_CMT_Start_ADDR 0x7500
< .DEFINE P_CMT_Ctrl_ADDR 0x7501
< .DEFINE P_CMT0_TCNT_ADDR 0x7508
< .DEFINE P_CMT1_TCNT_ADDR 0x7509
< .DEFINE P_CMT0_TPR_ADDR 0x7510
< .DEFINE P_CMT1_TPR_ADDR 0x7511
<
< //***************************************************************************//
< //***************************************************************************//
< // I. Time Base Register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_TMB_Reset_ADDR 0x70B8
< .DEFINE P_BZO_Ctrl_ADDR 0x70B9
<
<
<
<
< //========================================================================================
< //Constant Definition
< //========================================================================================
< // Timer Base Setup --- [P_TimeBase_Setup]
< .define C_TMBDIS 0x0010 //Disable TimeBase
< .define C_TMBENB 0x0000 //Enable TimeBase
< .define C_TMB2FS_128HZ 0x0000 //Set TimeBase2 as 128 HZ
< .define C_TMB2FS_256HZ 0x0004 //Set TimeBase2 as 256 HZ
< .define C_TMB2FS_512HZ 0x0008 //Set TimeBase2 as 512 HZ
< .define C_TMB2FS_1024HZ 0x000C //Set TimeBase2 as 1024 HZ
< .define C_TMB1FS_8HZ 0x0000 //Set TimeBase1 as 8 HZ
< .define C_TMB1FS_16HZ 0x0001 //Set TimeBase1 as 16 HZ
< .define C_TMB1FS_32HZ 0x0002 //Set TimeBase1 as 32 HZ
< .define C_TMB1FS_64HZ 0x0003 //Set TimeBase1 as 64 HZ
<
< //=================================//
< // flash control register //
< //=================================//
<
< // P_Wait_Enter register //
< // word set //
< .DEFINE CW_WaitCMD 0x5005
< .DEFINE CW_WaitClr 0x0001
<
< // P_Stdby_Enter register //
< // word set //
< .DEFINE CW_StdbyCMD 0xA00A
< .DEFINE CW_StdbyClr 0x0001
<
< // P_System_Option register //
< // word set //
< .DEFINE CW_SYS_CLK_R 0x0000
< .DEFINE CW_SYS_CLK_OSC 0x0001
<
< .DEFINE CW_SYS_WDG_Disable (0x0000 << 1)
< .DEFINE CW_SYS_WDG_Enable (0x0001 << 1)
<
< .DEFINE CW_SYS_LVR_Disable (0x0000 << 2)
< .DEFINE CW_SYS_LVR_Enable (0x0001 << 2)
<
< .DEFINE CW_SYS_LVD_Disable (0x0000 << 3)
< .DEFINE CW_SYS_LVD_Enable (0x0001 << 3)
<
< .DEFINE CW_SYS_Security_Protect (0x0000 << 4)
< .DEFINE CW_SYS_Security_NoProtect (0x0001 << 4)
<
< .DEFINE CW_SYS_Verification (0x02AA << 5)
<
<
< // P_Reset_Status register //
< // word set //
< .DEFINE CW_CLEAR_EXTRF 0x0001
< .DEFINE CW_CLEAR_PORF (0x0001 << 1)
< .DEFINE CW_CLEAR_WDRF (0x0001 << 2)
< .DEFINE CW_CLEAR_LPLVRF (0x0001 << 3)
< .DEFINE CW_CLEAR_SPLVRF (0x0001 << 4)
< .DEFINE CW_CLEAR_IARF (0x0001 << 5)
< .DEFINE CW_CLEAR_IIRF (0x0001 << 6)
< .DEFINE CW_CLEAR_FCHK (0x0055 << 9)
<
< // P_Clk_Ctrl register //
< // word set //
< .DEFINE CW_CLK_OSCIE (0x0001 << 14)
< .DEFINE CW_CLK_OSCSF (0x0001 << 15)
<
< // P_WatchDog_Ctrl register //
< // word set //
< .DEFINE CW_WDPS_FCKdiv65536 0x0000
< .DEFINE CW_WDPS_FCKdiv32768 0x0001
< .DEFINE CW_WDPS_FCKdiv16384 0x0002
< .DEFINE CW_WDPS_FCKdiv8192 0x0003
< .DEFINE CW_WDPS_FCKdiv4096 0x0004
< .DEFINE CW_WDPS_FCKdiv2048 0x0005
< .DEFINE CW_WDPS_FCKdiv1024 0x0006
< .DEFINE CW_WDPS_FCKdiv512 0x0007
<
< .DEFINE CW_WDCHK_Setting (0x0015 << 3)
< .DEFINE CW_WDRS_SYS_Reset (0x0000 << 14)
< .DEFINE CW_WDRS_CPU_Reset (0x0001 << 14)
< .DEFINE CW_WDEN (0x0001 << 15)
<
< .DEFINE CW_WatchDog_Clear 0xA005
<
< // P_Wakeup_Ctrl register //
< // word set //
< .DEFINE CW_CMTWE_Enable (0x0001<<4)
< .DEFINE CW_TPM0WE_Enable (0x0001<<5)
< .DEFINE CW_TPM1WE_Enable (0x0001<<6)
< .DEFINE CW_TPM2WE_Enable (0x0001<<7)
< .DEFINE CW_EXT0WE_Enable (0x0001<<11)
< .DEFINE CW_EXT1WE_Enable (0x0001<<12)
< .DEFINE CW_SPIWE_Enable (0x0001<<13)
< .DEFINE CW_UARTWE_Enable (0x0001<<14)
< .DEFINE CW_KEYWE_Enable (0x0001<<15)
<
<
< // P_Flash_RW register //
< // word set //
< .DEFINE CW_BK15WDIS 0x4000 //BANK 15 Write Disable
< .DEFINE CW_BK14WDIS 0x4000 //BANK 14 Write Disable
< .DEFINE CW_BK13WDIS 0x2000 //BANK 13 Write Disable
< .DEFINE CW_BK12WDIS 0x1000 //BANK 12 Write Disable
< .DEFINE CW_BK11WDIS 0x0800 //BANK 11 Write Disable
< .DEFINE CW_BK10WDIS 0x0400 //BANK 10 Write Disable
< .DEFINE CW_BK9WDIS 0x0200 //BANK 9 Write Disable
< .DEFINE CW_BK8WDIS 0x0100 //BANK 8 Write Disable
< .DEFINE CW_BK7WDIS 0x0080 //BANK 7 Write Disable
< .DEFINE CW_BK6WDIS 0x0040 //BANK 6 Write Disable
< .DEFINE CW_BK5WDIS 0x0020 //BANK 5 Write Disable
< .DEFINE CW_BK4WDIS 0x0010 //BANK 4 Write Disable
< .DEFINE CW_BK3WDIS 0x0008 //BANK 3 Write Disable
< .DEFINE CW_BK2WDIS 0x0004 //BANK 2 Write Disable
< .DEFINE CW_BK1WDIS 0x0002 //BANK 1 Write Disable
< .DEFINE CW_BK0WDIS 0x0001 //BANK 0 Write Disable
<
< // P_Flash_Ctrl register //
< // word set //
< .DEFINE CW_FlashRW_CMD 0x5A5A //Flash RW Command
< .DEFINE CW_FlashCMD 0xAAAA //Flash Command FLash Block
< .DEFINE CW_PageErase 0x5511 //Flash Page Erase Command
< .DEFINE CW_Program 0x5533 //Flash Program Command
< .DEFINE CW_Sequential 0x5544 //Flash Sequential Program Command
< .DEFINE CW_SequentialEnd 0xFFFF //Flash Sequential Program End Command
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