📄 spwm_am_sin_tab.lst
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Sunplus u'nSP Assembler - Ver. 1.12.2
Listing File Has Been Relocated
//========================================================================
// The information contained herein is the exclusive property of
// Sunplus Technology Co. And shall not be distributed, reproduced,
// or disclosed in whole in part without prior written permission.
// (C) COPYRIGHT 2001 SUNPLUS TECHNOLOGY CO.
// ALL RIGHTS RESERVED
// The entire notice above must be reproduced on all authorized copies.
//========================================================================
//========================================================================
// Filename: SPWM_AM_sin_TAB.asm
// Author: Lianshu Mou (email: Lianshu@sunnorth.com.cn)
// Date: 2004/08/05
// Description:
//
// Reference:
// Revision:
// 2004/08/05 First version
//========================================================================
.INCLUDE Spmc75_regs.inc
< // ========================================================================= //
< // File Name : Spmc75_regs.inc //
< // Description : SPMC75 series register definition //
< // Processor : SPMC751FM0A //
< // Author : laninlin //
< // Date : May 3 2004 //
< // Tools : u'nSP IDE tools v1.14.1 //
< // Version : 1.00 //
< // Security : Confidential Proprietary //
< // E-Mail : laninlin@sunplus.com.tw //
< // Revision : v1.00, Rease Version 2004/05/03 //
< // ========================================================================= //
< //***************************************************************************//
< // A. CPU control register //
< //****************************************************************************//
< //****************************************************************************//
< .DEFINE P_System_Option_ADDR 0x8000
< .DEFINE P_Wait_Enter_ADDR 0x700C
< .DEFINE P_Stdby_Enter_ADDR 0x700E
< .DEFINE P_Reset_Status_ADDR 0x7006
< .DEFINE P_Clk_Ctrl_ADDR 0x7007
< .DEFINE P_WatchDog_Ctrl_ADDR 0x700A
< .DEFINE P_WatchDog_Clr_ADDR 0x700B
< .DEFINE P_Wakeup_Ctrl_ADDR 0x700F
< .DEFINE P_INT_Status_ADDR 0x70A0
< .DEFINE P_INT_Priority_ADDR 0x70A4
< .DEFINE P_MisINT_Ctrl_ADDR 0x70A8
<
< //***************************************************************************//
< //***************************************************************************//
< // B. I/O Port register //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_IOA_Data_ADDR 0x7060
< .DEFINE P_IOA_Buffer_ADDR 0x7061
< .DEFINE P_IOA_Dir_ADDR 0x7062
< .DEFINE P_IOA_Attrib_ADDR 0x7063
< .DEFINE P_IOA_Latch_ADDR 0x7064
< .DEFINE P_IOA_SPE_ADDR 0x7080
< .DEFINE P_IOA_KCER_ADDR 0x7084
<
< .DEFINE P_IOB_Data_ADDR 0x7068
< .DEFINE P_IOB_Buffer_ADDR 0x7069
< .DEFINE P_IOB_Dir_ADDR 0x706A
< .DEFINE P_IOB_Attrib_ADDR 0x706B
< .DEFINE P_IOB_Latch_ADDR 0x706C
< .DEFINE P_IOB_SPE_ADDR 0x7081
<
< .DEFINE P_IOC_Data_ADDR 0x7070
< .DEFINE P_IOC_Buffer_ADDR 0x7071
< .DEFINE P_IOC_Dir_ADDR 0x7072
< .DEFINE P_IOC_Attrib_ADDR 0x7073
< .DEFINE P_IOC_Latch_ADDR 0x7074
< .DEFINE P_IOC_SPE_ADDR 0x7082
<
< .DEFINE P_IOD_Data_ADDR 0x7078
< .DEFINE P_IOD_Buffer_ADDR 0x7079
< .DEFINE P_IOD_Dir_ADDR 0x707A
< .DEFINE P_IOD_Attrib_ADDR 0x707B
< .DEFINE P_IOD_Latch_ADDR 0x707C
<
< //***************************************************************************//
< //***************************************************************************//
< // C. Timer 0,Timer 1,Timer 2,Timer 3,Timer 4 //
< //***************************************************************************//
< //***************************************************************************//
< .DEFINE P_TMR0_Ctrl_ADDR 0x7400
< .DEFINE P_TMR1_Ctrl_ADDR 0x7401
< .DEFINE P_TMR2_Ctrl_ADDR 0x7402
< .DEFINE P_TMR3_Ctrl_ADDR 0x7403
< .DEFINE P_TMR4_Ctrl_ADDR 0x7404
<
< .DEFINE P_TMR_LDOK_ADDR 0x740A
<
< .DEFINE P_TMR0_TCNT_ADDR 0x7430
< .DEFINE P_TMR1_TCNT_ADDR 0x7431
< .DEFINE P_TMR2_TCNT_ADDR 0x7432
< .DEFINE P_TMR3_TCNT_ADDR 0x7433
< .DEFINE P_TMR4_TCNT_ADDR 0x7434
<
< .DEFINE P_TMR0_TGRA_ADDR 0x7440
< .DEFINE P_TMR0_TGRB_ADDR 0x7441
< .DEFINE P_TMR0_TGRC_ADDR 0x7442
<
< .DEFINE P_TMR1_TGRA_ADDR 0x7443
< .DEFINE P_TMR1_TGRB_ADDR 0x7444
< .DEFINE P_TMR1_TGRC_ADDR 0x7445
<
< .DEFINE P_TMR2_TGRA_ADDR 0x7446
< .DEFINE P_TMR2_TGRB_ADDR 0x7447
<
< .DEFINE P_TMR3_TGRA_ADDR 0x7448
< .DEFINE P_TMR3_TGRB_ADDR 0x7449
< .DEFINE P_TMR3_TGRC_ADDR 0x744A
< .DEFINE P_TMR3_TGRD_ADDR 0x744B
<
< .DEFINE P_TMR4_TGRA_ADDR 0x744C
< .DEFINE P_TMR4_TGRB_ADDR 0x744D
< .DEFINE P_TMR4_TGRC_ADDR 0x744E
< .DEFINE P_TMR4_TGRD_ADDR 0x744F
<
< .DEFINE P_TMR0_TPR_ADDR 0x7435
< .DEFINE P_TMR1_TPR_ADDR 0x7436
< .DEFINE P_TMR2_TPR_ADDR 0x7437
< .DEFINE P_TMR3_TPR_ADDR 0x7438
< .DEFINE P_TMR4_TPR_ADDR 0x7439
<
< .DEFINE P_TMR0_TBRA_ADDR 0x7450
< .DEFINE P_TMR0_TBRB_ADDR 0x7451
< .DEFINE P_TMR0_TBRC_ADDR 0x7452
<
< .DEFINE P_TMR1_TBRA_ADDR 0x7453
< .DEFINE P_TMR1_TBRB_ADDR 0x7454
< .DEFINE P_TMR1_TBRC_ADDR 0x7455
<
< .DEFINE P_TMR2_TBRA_ADDR 0x7456
< .DEFINE P_TMR2_TBRB_ADDR 0x7457
<
< .DEFINE P_TMR3_TBRA_ADDR 0x7458
< .DEFINE P_TMR3_TBRB_ADDR 0x7459
< .DEFINE P_TMR3_TBRC_ADDR 0x745A
<
< .DEFINE P_TMR4_TBRA_ADDR 0x745C
< .DEFINE P_TMR4_TBRB_ADDR 0x745D
< .DEFINE P_TMR4_TBRC_ADDR 0x745E
<
< .DEFINE P_TMR0_IOCtrl_ADDR 0x7410
< .DEFINE P_TMR1_IOCtrl_ADDR 0x7411
< .DEFINE P_TMR2_IOCtrl_ADDR 0x7412
< .DEFINE P_TMR3_IOCtrl_ADDR 0x7413
< .DEFINE P_TMR4_IOCtrl_ADDR 0x7414
<
< .DEFINE P_TMR0_INT_ADDR 0x7420
< .DEFINE P_TMR1_INT_ADDR 0x7421
< .DEFINE P_TMR2_INT_ADDR 0x7422
< .DEFINE P_TMR3_INT_ADDR 0x7423
< .DEFINE P_TMR4_INT_ADDR 0x7424
<
< .DEFINE P_TMR0_Status_ADDR 0x7425
< .DEFINE P_TMR1_Status_ADDR 0x7426
< .DEFINE P_TMR2_Status_ADDR 0x7427
< .DEFINE P_TMR3_Status_ADDR 0x7428
< .DEFINE P_TMR4_Status_ADDR 0x7429
<
< .DEFINE P_TMR_Start_ADDR 0x7405
< .DEFINE P_TMR_Output_ADDR 0x7406
<
< .DEFINE P_TMR3_OutputCtrl_ADDR 0x7407
< .DEFINE P_TMR4_OutputCtrl_ADDR 0x7408
<
< .DEFINE P_POS0_DectCtrl_ADDR 0x7462
< .DEFINE P_POS1_DectCtrl_ADDR 0x7463
<
< .DEFINE P_POS0_DectData_ADDR 0x7464
< .DEFINE P_POS1_DectData_ADDR 0x7465
<
< .DEFINE P_TMR3_DeadTime_ADDR 0x7460
< .DEFINE P_TMR4_DeadTime_ADDR 0x7461
<
< .DEFINE P_TPWM_Write_ADDR 0x7409
<
< .DEFINE P_TMR3_FaultCtrl_ADDR 0x7466
< .DEFINE P_TMR4_FaultCtrl_ADDR 0x7467
<
< .DEFINE P_TMR3_OLProtect_ADDR 0x7468
< .DEFINE P_TMR4_OLProtect_ADDR 0x7469
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