mlibif.c

Atheros AP Test with Agilent N4010A source code

/* MLIBif.c - contians wrapper functions for MLIB */

/* Copyright (c) 2000 Atheros Communications, Inc., All Rights Reserved */
#ident  "ACI $Id: //depot/sw/branches/ART_V53_dragon/sw/src/dk/mdk/devmld/MLIBif.c#2 $, $Header: //depot/sw/branches/ART_V53_dragon/sw/src/dk/mdk/devmld/MLIBif.c#2 $"

#ifdef _WINDOWS 
#include <windows.h>
#endif

#include <time.h>
#include <errno.h>
#include <stdio.h>
#include "wlantype.h"
#include "athreg.h"
#include "manlib.h"
#include "manlibInst.h"
#include "dk_ver.h"
#include "common_hw.h"
#ifdef JUNGO
#include "mld.h"
#endif
#include "MLIBif.h"
#include "art_if.h"
#include <stdlib.h>

#ifdef LINUX
#include <string.h>
#endif

// Dev to driverDev mapping table.  devNum must be in range 0 to LIB_MAX_DEV
A_UINT32   devNum2driverTable[LIB_MAX_DEV];
extern A_BOOL thin_client;
static A_BOOL last_op_was_read = 0;
static A_BOOL last_op_offset_was_fc = 0;

static void printRxStats(RX_STATS_STRUCT *pRxStats);
static void printTxStats(TX_STATS_STRUCT *pTxStats);

A_UCHAR *t_bytesRead;
A_UCHAR *t_bytesWrite;

A_BOOL initializeEnvironment(A_BOOL remote) {
	A_BOOL	openDriver;
  
    // print version string
    uiPrintf("\n    --- Atheros Radio Test (ART) ---\n");
    uiPrintf(MAUIDK_VER2);
    uiPrintf(MAUIDK_VER3);
 
	openDriver = remote ?  0 : 1;

    // perform environment initialization
#ifdef _DEBUG
    if ( A_ERROR == envInit(TRUE, openDriver) ) {
#else
    if ( A_ERROR == envInit(FALSE, openDriver) ) {
#endif
        uiPrintf("Error: Unable to initialize the local environment... Closing down!\n");
        return FALSE;
    }
	t_bytesRead = (A_UCHAR *) malloc(MAX_MEMREAD_BYTES * sizeof(A_UCHAR));
	t_bytesWrite = (A_UCHAR *) malloc(MAX_MEMREAD_BYTES * sizeof(A_UCHAR));
	if ((t_bytesRead == NULL) || (t_bytesWrite == NULL)) 	
		return FALSE;
    return TRUE;
}


void closeEnvironment(void) {
    // clean up anything that was allocated and close the local driver
    envCleanup(TRUE);
	if (t_bytesRead != NULL) 
			free(t_bytesRead);
	if (t_bytesWrite != NULL) 
			free(t_bytesWrite);
}

A_BOOL devNumValid
(
 A_UINT32 devNum
)
{
    if(globDrvInfo.pDevInfoArray[dev2drv(devNum)] != NULL) {
        return TRUE;
    }
    else {
        return FALSE;
    }
}

void txPrintStats
(
 A_UINT32 devNum, 
 A_UINT32 rateInMb,
 A_UINT32 remote
)
{
    TX_STATS_STRUCT rStats;

    txGetStats(devNum, rateInMb, remote, &rStats);

	//check for errors
    if (!getMdkErrNo(devNum)) {
	    printTxStats(&rStats);
    }
}

void printTxStats
(
 TX_STATS_STRUCT *pTxStats
)
{
	uiPrintf("Good Packets           %10lu  ", pTxStats->goodPackets);
	uiPrintf("Ack sig strnth min     %10lu\n", pTxStats->ackSigStrengthMin);
	uiPrintf("Underruns              %10lu  ", pTxStats->underruns);
	uiPrintf("Ack sig strenth avg    %10lu\n", pTxStats->ackSigStrengthAvg);
	uiPrintf("Throughput             %10.2f  ",(float) pTxStats->throughput/1000);
	uiPrintf("Ack sig strenth max    %10lu\n", pTxStats->ackSigStrengthMax);
	uiPrintf("Excess retries         %10lu  ", pTxStats->excessiveRetries);
	uiPrintf("short retries 4        %10lu\n", pTxStats->shortRetry4); 
	uiPrintf("short retries 1        %10lu  ", pTxStats->shortRetry1); 
	uiPrintf("short retries 5        %10lu\n", pTxStats->shortRetry5); 
	uiPrintf("short retries 2        %10lu  ", pTxStats->shortRetry2); 
	uiPrintf("short retries 6-10     %10lu\n", pTxStats->shortRetry6to10); 
	uiPrintf("short retries 3        %10lu  ", pTxStats->shortRetry3); 
	uiPrintf("short retries 11-15    %10lu\n", pTxStats->shortRetry11to15); 
/*	uiPrintf("long  retries 1        %10lu  ", pTxStats->longRetry1); 
	uiPrintf("long  retries 2        %10lu\n", pTxStats->longRetry2); 
	uiPrintf("long  retries 3        %10lu  ", pTxStats->longRetry3); 
	uiPrintf("long  retries 4        %10lu\n", pTxStats->longRetry4); 
	uiPrintf("long  retries 5        %10lu  ", pTxStats->longRetry5); 
	uiPrintf("long  retries 6-10     %10lu\n", pTxStats->longRetry6to10); 
	uiPrintf("long  retries 11-15    %10lu\n", pTxStats->longRetry11to15);  */
}

void rxPrintStats
(
 A_UINT32 devNum,
 A_UINT32 rateInMb,
 A_UINT32 remote
)
{
    RX_STATS_STRUCT rStats;

    rxGetStats(devNum, rateInMb, remote, &rStats);

	//check for errors
    if (!getMdkErrNo(devNum)) {
	    printRxStats(&rStats);
    }

}

void printRxStats
(
 RX_STATS_STRUCT *pRxStats
)
{
	uiPrintf("Good Packets           %10lu  ", pRxStats->goodPackets);
	uiPrintf("Data sig strenth min   %10lu\n", pRxStats->DataSigStrengthMin);
	uiPrintf("CRC-Failure Packets    %10lu  ", pRxStats->crcPackets);
	uiPrintf("Data sig strenth avg   %10lu\n", pRxStats->DataSigStrengthAvg);
	uiPrintf("Bad CRC Miscomps       %10lu  ", pRxStats->bitMiscompares);
	uiPrintf("Data sig strenth max   %10lu\n", pRxStats->DataSigStrengthMax);
	uiPrintf("Good Packet Miscomps   %10lu  ", pRxStats->bitErrorCompares);
	uiPrintf("PPM min                %10ld\n", pRxStats->ppmMin);
	uiPrintf("Single dups            %10lu  ", pRxStats->singleDups);
	uiPrintf("PPM avg                %10ld\n", pRxStats->ppmAvg);
	uiPrintf("Multiple dups          %10lu  ", pRxStats->multipleDups);
	uiPrintf("PPM max                %10ld\n", pRxStats->ppmMax);
	return;
}

/**************************************************************************
 * Workaround for HW bug that causes read or write bursts that
 * cross a 256-boundary to access the incorrect register.
 */  
static void
reg_burst_war
(
	A_UINT16 devIndex,
	A_UINT32 offset, 
	A_BOOL op_is_read
)
{
    A_UINT32 offset_lsb;
	MDK_WLAN_DEV_INFO *pdevInfo;
	
    offset_lsb = offset & 0xff;
	pdevInfo = globDrvInfo.pDevInfoArray[devIndex];

    // Check if offset is aligned to a 256-byte boundary
    if (offset_lsb == 0) {
      if (last_op_offset_was_fc && (last_op_was_read == op_is_read)) {
         // Last access was to an offset with lsbs of 0xfc and was
         // of the same type (read or write) as the current access, so
         // need to break a possible burst across the 256-byte boundary.
         // Do this by reading the SREV reg, as it's always safe to do so.
         hwMemRead32(devIndex, 0x4020 + pdevInfo->pdkInfo->f2MapAddress);
      }
    }
  
    last_op_was_read = op_is_read;
    last_op_offset_was_fc = (offset_lsb == 0xfc);
}

/**************************************************************************
* OSregRead - MLIB command for reading a register
*
* RETURNS: value read
*/
A_UINT32 OSregRead
(
    A_UINT32 devNum,
    A_UINT32 regOffset
)
{
    A_UINT32         regReturn;
    MDK_WLAN_DEV_INFO    *pdevInfo;
	A_UINT16 devIndex;

	if(devNumValid(devNum) == FALSE) {
		uiPrintf("Error: OSregRead did not receive a valid devNum\n");
	    return(0xdeadbeef);
	}

	devIndex = (A_UINT16)dev2drv(devNum);
   	pdevInfo = globDrvInfo.pDevInfoArray[devIndex];

  if (thin_client) {
        regOffset -= pdevInfo->pdkInfo->aregPhyAddr[0];
        regReturn = art_regRead(devNum, regOffset);
  }
  else {
   	/* check that the register is within the range of registers */
	if( (regOffset < pdevInfo->pdkInfo->f2MapAddress) || 
		(regOffset > (MAX_REG_OFFSET + pdevInfo->pdkInfo->f2MapAddress)) ) {
		uiPrintf("Error:  OSregRead Not a valid register offset:%x\n", regOffset);
		return(0xdeadbeef);
    }

	/* read the register */
	reg_burst_war(devIndex, regOffset, 1);
	regReturn = hwMemRead32(devIndex, regOffset); 
	// uiPrintf("Register at offset %08lx: %08lx\n", regOffset, regReturn);
    //
  }

    return(regReturn);
}


/**************************************************************************
* OSregWrite - MLIB command for writing a register
*
*/
void OSregWrite
(
	A_UINT32 devNum,
    A_UINT32 regOffset,
    A_UINT32 regValue
)
{
    MDK_WLAN_DEV_INFO    *pdevInfo;
	A_UINT16 devIndex;

	if(devNumValid(devNum) == FALSE) {
		uiPrintf("Error: OSregWrite did not receive a valid devNum\n");
		return;
	}

	devIndex = (A_UINT16)dev2drv(devNum);
   	pdevInfo = globDrvInfo.pDevInfoArray[devIndex];
	if (thin_client) {
       regOffset -= pdevInfo->pdkInfo->aregPhyAddr[0];
       art_regWrite(devNum, regOffset, regValue);
	   if(pdevInfo->pdkInfo->printPciWrites) 
	   {
		uiPrintf("0x%04x 0x%08x\n", regOffset & 0xffff, regValue);
	   } 
	}
	else {

//    regOffset += pdevInfo->pdkInfo->aregPhyAddr[0];

	  if( (regOffset < pdevInfo->pdkInfo->f2MapAddress) || 
		(regOffset > (MAX_REG_OFFSET + pdevInfo->pdkInfo->f2MapAddress)) ) {
		uiPrintf("Error:  OSregWrite Not a valid register offset\n");
		return;
      }

	  /* write the register */
	  reg_burst_war(devIndex, regOffset, 0);
	  hwMemWrite32(devIndex, regOffset, regValue); 
	  if(pdevInfo->pdkInfo->printPciWrites) 
	  {
		uiPrintf("0x%04x 0x%08x\n", regOffset & 0xffff, regValue);
	  } 
	}
}


/**************************************************************************
* OScfgRead - MLIB command for reading a pci configuration register
*
* RETURNS: value read
*/
A_UINT32 OScfgRead
(
	A_UINT32 devNum,
    A_UINT32 regOffset
)
{
    A_UINT32         regReturn;
	A_UINT16 devIndex;

	if(devNumValid(devNum) == FALSE) {
		uiPrintf("Error: OScfgRead did not receive a valid devNum\n");
	    return(0xdeadbeef);
	}

	if (thin_client) {
       regReturn = art_cfgRead(devNum, regOffset);
	}
	else {
	   devIndex = (A_UINT16)dev2drv(devNum);

	   if(regOffset > MAX_CFG_OFFSET) {
		   uiPrintf("Error:  OScfgRead: not a valid config offset\n");
		   return(0xdeadbeef);
       }
	   regReturn = hwCfgRead32(devIndex, regOffset); 

       /* display the value */
       //uiPrintf("%08lx: ", regOffset);
       //uiPrintf("%08lx\n", regReturn);
	}

    return(regReturn);
}

/**************************************************************************
* OScfgWrite - MLIB command for writing a pci config register
*
*/
void OScfgWrite
(
	A_UINT32 devNum,
    A_UINT32 regOffset,
    A_UINT32 regValue
)
{
	A_UINT16 devIndex;
   
	if(devNumValid(devNum) == FALSE) {
		uiPrintf("Error: OScfgWrite did not receive a valid devNum\n");
		return;
	}