dk.pm

Atheros AP Test with Agilent N4010A source code

# This file was automatically generated by SWIG
package dk;
require Exporter;
@ISA = qw(Exporter);
package dkc;
boot_dk();
package dk;
@EXPORT = qw( $F2_CR $F2_CR_RXE $F2_CR_RXD $F2_CR_SWI $F2_RXDP $F2_CFG $F2_CFG_SWTD $F2_CFG_SWTB $F2_CFG_SWRD $F2_CFG_SWRB $F2_CFG_SWRG $F2_CFG_AP_ADHOC_INDICATION $F2_CFG_PHOK $F2_CFG_EEBS $F2_CFG_PCI_MASTER_REQ_Q_THRESH_M $F2_CFG_PCI_MASTER_REQ_Q_THRESH_S $F2_IER $F2_IER_ENABLE $F2_IER_DISABLE $F2_RTSD0 $F2_RTSD0_RTS_DURATION_6_M $F2_RTSD0_RTS_DURATION_6_S $F2_RTSD0_RTS_DURATION_9_M $F2_RTSD0_RTS_DURATION_9_S $F2_RTSD0_RTS_DURATION_12_M $F2_RTSD0_RTS_DURATION_12_S $F2_RTSD0_RTS_DURATION_18_M $F2_RTSD0_RTS_DURATION_18_S $F2_RTSD1 $F2_RTSD0_RTS_DURATION_24_M $F2_RTSD0_RTS_DURATION_24_S $F2_RTSD0_RTS_DURATION_36_M $F2_RTSD0_RTS_DURATION_36_S $F2_RTSD0_RTS_DURATION_48_M $F2_RTSD0_RTS_DURATION_48_S $F2_RTSD0_RTS_DURATION_54_M $F2_RTSD0_RTS_DURATION_54_S $F2_TXCFG $F2_TXCFG_CONT_EN $F2_RXCFG $F2_RXCFG_DEF_RX_ANTENNA $F2_RXCFG_ZLFDMA $F2_DMASIZE_4B $F2_DMASIZE_8B $F2_DMASIZE_16B $F2_DMASIZE_32B $F2_DMASIZE_64B $F2_DMASIZE_128B $F2_DMASIZE_256B $F2_DMASIZE_512B $F2_MIBC $F2_MIBC_COW $F2_MIBC_FMC $F2_MIBC_CMC $F2_MIBC_MCS $F2_TOPS $F2_TOPS_MASK $F2_RXNPTO $F2_RXNPTO_MASK $F2_TXNPTO $F2_TXNPTO_MASK $F2_TXNPTO_QCU_MASK $F2_RPGTO $F2_RPGTO_MASK $F2_RPCNT $F2_RPCNT_MASK $F2_MACMISC $F2_MACMISC_DMA_OBS_M $F2_MACMISC_DMA_OBS_S $F2_MACMISC_MISC_OBS_M $F2_MACMISC_MISC_OBS_S $F2_MACMISC_MAC_OBS_BUS_LSB_M $F2_MACMISC_MAC_OBS_BUS_LSB_S $F2_MACMISC_MAC_OBS_BUS_MSB_M $F2_MACMISC_MAC_OBS_BUS_MSB_S $F2_QDCKLGATE $F2_QDCKLGATE_QCU_M $F2_QDCKLGATE_DCU_M $F2_ISR $F2_ISR_RXOK $F2_ISR_RXDESC $F2_ISR_RXERR $F2_ISR_RXNOPKT $F2_ISR_RXEOL $F2_ISR_RXORN $F2_ISR_TXOK $F2_ISR_TXDESC $F2_ISR_TXERR $F2_ISR_TXNOPKT $F2_ISR_TXEOL $F2_ISR_TXURN $F2_ISR_MIB $F2_ISR_SWI $F2_ISR_RXPHY $F2_ISR_RXKCM $F2_ISR_SWBA $F2_ISR_BRSSI $F2_ISR_BMISS $F2_ISR_HIUERR $F2_ISR_BNR $F2_ISR_TIM $F2_ISR_GPIO $F2_ISR_QCBROVF $F2_ISR_QCBRURN $F2_ISR_QTRIG $F2_ISR_RESV0 $F2_ISR_S0 $F2_ISR_S0_QCU_TXOK_M $F2_ISR_S0_QCU_TXDESC_M $F2_ISR_S1 $F2_ISR_S1_QCU_TXERR_M $F2_ISR_S1_QCU_TXEOL_M $F2_ISR_S2 $F2_ISR_S2_QCU_TXURN_M $F2_ISR_S2_MCABT $F2_ISR_S2_SSERR $F2_ISR_S2_DPERR $F2_ISR_S2_RESV0 $F2_ISR_S3 $F2_ISR_S3_QCU_QCBROVF_M $F2_ISR_S3_QCU_QCBRURN_M $F2_ISR_S4 $F2_ISR_S4_QCU_QTRIG_M $F2_ISR_S4_RESV0 $F2_IMR $F2_IMR_RXOK $F2_IMR_RXDESC $F2_IMR_RXERR $F2_IMR_RXNOPKT $F2_IMR_RXEOL $F2_IMR_RXORN $F2_IMR_TXOK $F2_IMR_TXDESC $F2_IMR_TXERR $F2_IMR_TXNOPKT $F2_IMR_TXEOL $F2_IMR_TXURN $F2_IMR_MIB $F2_IMR_SWI $F2_IMR_RXPHY $F2_IMR_RXKCM $F2_IMR_SWBA $F2_IMR_BRSSI $F2_IMR_BMISS $F2_IMR_HIUERR $F2_IMR_BNR $F2_IMR_TIM $F2_IMR_GPIO $F2_IMR_QCBROVF $F2_IMR_QCBRURN $F2_IMR_QTRIG $F2_IMR_RESV0 $F2_IMR_S0 $F2_IMR_S0_QCU_TXOK_M $F2_IMR_S0_QCU_TXDESC_M $F2_IMR_S0_QCU_TXDESC_S $F2_IMR_S1 $F2_IMR_S1_QCU_TXERR_M $F2_IMR_S1_QCU_TXEOL_M $F2_IMR_S1_QCU_TXEOL_S $F2_IMR_S2 $F2_IMR_S2_QCU_TXURN_M $F2_IMR_S2_MCABT $F2_IMR_S2_SSERR $F2_IMR_S2_DPERR $F2_IMR_S2_RESV0 $F2_IMR_S3 $F2_IMR_S3_QCU_QCBROVF_M $F2_IMR_S3_QCU_QCBRURN_M $F2_IMR_S3_QCU_QCBRURN_S $F2_IMR_S4 $F2_IMR_S4_QCU_QTRIG_M $F2_IMR_S4_RESV0 $F2_ISR_RAC $F2_ISR_S0_S $F2_ISR_S1_S $F2_ISR_S2_S $F2_ISR_S3_S $F2_ISR_S4_S $F2_NUM_QCU $F2_QCU_0 $F2_QCU_1 $F2_QCU_2 $F2_QCU_3 $F2_QCU_4 $F2_QCU_5 $F2_QCU_6 $F2_QCU_7 $F2_QCU_8 $F2_QCU_9 $F2_QCU_10 $F2_QCU_11 $F2_QCU_12 $F2_QCU_13 $F2_QCU_14 $F2_QCU_15 $F2_Q0_TXDP $F2_Q1_TXDP $F2_Q2_TXDP $F2_Q3_TXDP $F2_Q4_TXDP $F2_Q5_TXDP $F2_Q6_TXDP $F2_Q7_TXDP $F2_Q8_TXDP $F2_Q9_TXDP $F2_Q10_TXDP $F2_Q11_TXDP $F2_Q12_TXDP $F2_Q13_TXDP $F2_Q14_TXDP $F2_Q15_TXDP $F2_Q_TXE $F2_Q_TXE_M $F2_Q_TXD $F2_Q_TXD_M $F2_Q0_CBRCFG $F2_Q1_CBRCFG $F2_Q2_CBRCFG $F2_Q3_CBRCFG $F2_Q4_CBRCFG $F2_Q5_CBRCFG $F2_Q6_CBRCFG $F2_Q7_CBRCFG $F2_Q8_CBRCFG $F2_Q9_CBRCFG $F2_Q10_CBRCFG $F2_Q11_CBRCFG $F2_Q12_CBRCFG $F2_Q13_CBRCFG $F2_Q14_CBRCFG $F2_Q15_CBRCFG $F2_Q_CBRCFG_CBR_INTERVAL_M $F2_Q_CBRCFG_CBR_OVF_THRESH_M $F2_Q0_RDYTIMECFG $F2_Q1_RDYTIMECFG $F2_Q2_RDYTIMECFG $F2_Q3_RDYTIMECFG $F2_Q4_RDYTIMECFG $F2_Q5_RDYTIMECFG $F2_Q6_RDYTIMECFG $F2_Q7_RDYTIMECFG $F2_Q8_RDYTIMECFG $F2_Q9_RDYTIMECFG $F2_Q10_RDYTIMECFG $F2_Q11_RDYTIMECFG $F2_Q12_RDYTIMECFG $F2_Q13_RDYTIMECFG $F2_Q14_RDYTIMECFG $F2_Q15_RDYTIMECFG $F2_Q_RDYTIMECFG_DURATION_M $F2_Q_RDYTIMECFG_EN $F2_Q_RDYTIMECFG_RESV0 $F2_Q_ONESHOTARM_SC $F2_Q_ONESHOTARM_SC_M $F2_Q_ONESHOTARM_SC_RESV0 $F2_Q_ONESHOTARM_CC $F2_Q_ONESHOTARM_CC_M $F2_Q_ONESHOTARM_CC_RESV0 $F2_Q0_MISC $F2_Q1_MISC $F2_Q2_MISC $F2_Q3_MISC $F2_Q4_MISC $F2_Q5_MISC $F2_Q6_MISC $F2_Q7_MISC $F2_Q8_MISC $F2_Q9_MISC $F2_Q10_MISC $F2_Q11_MISC $F2_Q12_MISC $F2_Q13_MISC $F2_Q14_MISC $F2_Q15_MISC $F2_Q_MISC_FSP_M $F2_Q_MISC_FSP_ASAP $F2_Q_MISC_FSP_CBR $F2_Q_MISC_FSP_DBA_GATED $F2_Q_MISC_FSP_TIM_GATED $F2_Q_MISC_FSP_BEACON_SENT_GATED $F2_Q_MISC_ONE_SHOT_EN $F2_Q_MISC_CBR_INCR_DIS1 $F2_Q_MISC_CBR_INCR_DIS0 $F2_Q_MISC_BEACON_USE $F2_Q_MISC_CBR_EXP_CNTR_LIMIT $F2_Q_MISC_RDYTIME_EXP_POLICY $F2_Q_MISC_RESET_CBR_EXP_CTR $F2_Q_MISC_RESV0 $F2_Q0_STS $F2_Q1_STS $F2_Q2_STS $F2_Q3_STS $F2_Q4_STS $F2_Q5_STS $F2_Q6_STS $F2_Q7_STS $F2_Q8_STS $F2_Q9_STS $F2_Q10_STS $F2_Q11_STS $F2_Q12_STS $F2_Q13_STS $F2_Q14_STS $F2_Q15_STS $F2_Q_STS_PEND_FR_CNT_M $F2_Q_STS_RESV0 $F2_Q_STS_CBR_EXP_CNT_M $F2_Q_STS_RESV1 $F2_Q_RDYTIMESHDN $F2_Q_RDYTIMESHDN_M $F2_NUM_DCU $F2_DCU_0 $F2_DCU_1 $F2_DCU_2 $F2_DCU_3 $F2_DCU_4 $F2_DCU_5 $F2_DCU_6 $F2_DCU_7 $F2_DCU_8 $F2_DCU_9 $F2_DCU_10 $F2_DCU_11 $F2_D0_QCUMASK $F2_D1_QCUMASK $F2_D2_QCUMASK $F2_D3_QCUMASK $F2_D4_QCUMASK $F2_D5_QCUMASK $F2_D6_QCUMASK $F2_D7_QCUMASK $F2_D8_QCUMASK $F2_D9_QCUMASK $F2_D10_QCUMASK $F2_D_QCUMASK_M $F2_D_QCUMASK_RESV0 $F2_D0_LCL_IFS $F2_D1_LCL_IFS $F2_D2_LCL_IFS $F2_D3_LCL_IFS $F2_D4_LCL_IFS $F2_D5_LCL_IFS $F2_D6_LCL_IFS $F2_D7_LCL_IFS $F2_D8_LCL_IFS $F2_D9_LCL_IFS $F2_D10_LCL_IFS $F2_D_LCL_IFS_CWMIN_M $F2_D_LCL_IFS_CWMAX_M $F2_D_LCL_IFS_CWMAX_S $F2_D_LCL_IFS_AIFS_M $F2_D_LCL_IFS_AIFS_S $F2_D_LCL_IFS_RESV0 $F2_D0_RETRY_LIMIT $F2_D1_RETRY_LIMIT $F2_D2_RETRY_LIMIT $F2_D3_RETRY_LIMIT $F2_D4_RETRY_LIMIT $F2_D5_RETRY_LIMIT $F2_D6_RETRY_LIMIT $F2_D7_RETRY_LIMIT $F2_D8_RETRY_LIMIT $F2_D9_RETRY_LIMIT $F2_D10_RETRY_LIMIT $F2_D_RETRY_LIMIT_FR_SH_M $F2_D_RETRY_LIMIT_FR_LG_M $F2_D_RETRY_LIMIT_STA_SH_M $F2_D_RETRY_LIMIT_STA_LG_M $F2_D_RETRY_LIMIT_RESV0 $F2_D0_CHNTIME $F2_D1_CHNTIME $F2_D2_CHNTIME $F2_D3_CHNTIME $F2_D4_CHNTIME $F2_D5_CHNTIME $F2_D6_CHNTIME $F2_D7_CHNTIME $F2_D8_CHNTIME $F2_D9_CHNTIME $F2_D10_CHNTIME $F2_D_CHNTIME_DUR_M $F2_D_CHNTIME_EN $F2_D_CHNTIME_RESV0 $F2_D0_MISC $F2_D1_MISC $F2_D2_MISC $F2_D3_MISC $F2_D4_MISC $F2_D5_MISC $F2_D6_MISC $F2_D7_MISC $F2_D8_MISC $F2_D9_MISC $F2_D10_MISC $F2_D_MISC_BKOFF_THRESH_M $F2_D_MISC_HCF_POLL_EN $F2_D_MISC_BKOFF_PERSISTENCE $F2_D_MISC_FR_PREFETCH_EN $F2_D_MISC_VIR_COL_HANDLING_M $F2_D_MISC_VIR_COL_HANDLING_NORMAL $F2_D_MISC_VIR_COL_HANDLING_MODIFIED $F2_D_MISC_VIR_COL_HANDLING_IGNORE $F2_D_MISC_BEACON_USE $F2_D_MISC_ARB_LOCKOUT_CNTRL_M $F2_D_MISC_ARB_LOCKOUT_CNTRL_S $F2_D_MISC_ARB_LOCKOUT_CNTRL_NONE $F2_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR $F2_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL $F2_D_MISC_ARB_LOCKOUT_IGNORE $F2_D_MISC_SEQ_NUM_INCR_DIS $F2_D_MISC_POST_FR_BKOFF_DIS $F2_D_MISC_VIRT_COLL_POLICY $F2_D_MISC_BLOWN_IFS_POLICY $F2_D_MISC_SEQ_NUM_CONTROL $F2_D_MISC_RESV0 $F2_D0_SEQNUM $F2_D1_SEQNUM $F2_D2_SEQNUM $F2_D3_SEQNUM $F2_D4_SEQNUM $F2_D5_SEQNUM $F2_D6_SEQNUM $F2_D7_SEQNUM $F2_D8_SEQNUM $F2_D9_SEQNUM $F2_D10_SEQNUM $F2_D_SEQNUM_M $F2_D_SEQNUM_RESV0 $F2_D_GBL_IFS_SIFS $F2_D_GBL_IFS_SIFS_M $F2_D_GBL_IFS_SIFS_RESV0 $F2_D_GBL_IFS_SLOT $F2_D_GBL_IFS_SLOT_M $F2_D_GBL_IFS_SLOT_RESV0 $F2_D_GBL_IFS_EIFS $F2_D_GBL_IFS_EIFS_M $F2_D_GBL_IFS_EIFS_RESV0 $F2_D_GBL_IFS_MISC $F2_D_GBL_IFS_MISC_LFSR_SLICE_SEL_M $F2_D_GBL_IFS_MISC_TURBO_MODE $F2_D_GBL_IFS_MISC_SIFS_DURATION_USEC_M $F2_D_GBL_IFS_MISC_USEC_DURATION_M $F2_D_GBL_IFS_MISC_DCU_ARBITER_DLY_M $F2_D_GBL_IFS_MISC_RESV0 $F2_D_FPCTL $F2_D_TXBLK_BASE $F2_RC $F2_RC_MAC $F2_RC_BB $F2_RC_RESV0 $F2_RC_RESV1 $F2_RC_PCI $F2_SCR $F2_SCR_SLDUR_MASK $F2_SCR_SLE_MASK $F2_SCR_SLE_FWAKE $F2_SCR_SLE_FSLEEP $F2_SCR_SLE_NORMAL $F2_SCR_SLE_UNITS $F2_INTPEND $F2_INTPEND_TRUE $F2_SFR $F2_SFR_SLEEP $F2_SFR_WAKE $F2_PCICFG $F2_PCICFG_SLEEP_CLK_SEL $F2_PCICFG_CLKRUNEN $F2_PCICFG_EEPROM_SIZE_M $F2_PCICFG_EEPROM_SIZE_4K $F2_PCICFG_EEPROM_SIZE_8K $F2_PCICFG_EEPROM_SIZE_16K $F2_PCICFG_EEPROM_SIZE_FAILED $F2_PCICFG_ASSOC_STATUS_M $F2_PCICFG_ASSOC_STATUS_NONE $F2_PCICFG_ASSOC_STATUS_PENDING $F2_PCICFG_ASSOC_STATUS_ASSOCIATED $F2_PCICFG_PCI_BUS_SEL_M $F2_PCICFG_DIS_CBE_FIX $F2_PCICFG_SL_INTEN $F2_PCICFG_RESV0 $F2_PCICFG_SL_INPEN $F2_PCICFG_RESV1 $F2_PCICFG_SPWR_DN $F2_PCICFG_LED_MODE_M $F2_PCICFG_LED_BLINK_THRESHOLD_M $F2_PCICFG_LED_SLOW_BLINK_MODE $F2_PCICFG_SLEEP_CLK_RATE_INDICATION $F2_PCICFG_RESV2 $F2_NUM_GPIO $F2_GPIOCR $F2_GPIOCR_CR_SHIFT $F2_GPIOCR_0_CR_N $F2_GPIOCR_0_CR_0 $F2_GPIOCR_0_CR_1 $F2_GPIOCR_0_CR_A $F2_GPIOCR_1_CR_N $F2_GPIOCR_1_CR_0 $F2_GPIOCR_1_CR_1 $F2_GPIOCR_1_CR_A $F2_GPIOCR_2_CR_N $F2_GPIOCR_2_CR_0 $F2_GPIOCR_2_CR_1 $F2_GPIOCR_2_CR_A $F2_GPIOCR_3_CR_N $F2_GPIOCR_3_CR_0 $F2_GPIOCR_3_CR_1 $F2_GPIOCR_3_CR_A $F2_GPIOCR_4_CR_N $F2_GPIOCR_4_CR_0 $F2_GPIOCR_4_CR_1 $F2_GPIOCR_4_CR_A $F2_GPIOCR_5_CR_N $F2_GPIOCR_5_CR_0 $F2_GPIOCR_5_CR_1 $F2_GPIOCR_5_CR_A $F2_GPIOCR_INT_SEL0 $F2_GPIOCR_INT_SEL1 $F2_GPIOCR_INT_SEL2 $F2_GPIOCR_INT_SEL3 $F2_GPIOCR_INT_SEL4 $F2_GPIOCR_INT_SEL5 $F2_GPIOCR_INT_EN $F2_GPIOCR_INT_SELL $F2_GPIOCR_INT_SELH $F2_GPIODO $F2_GPIODI $F2_GPIOD_MASK $F2_SREV $F2_SREV_ID_M $F2_SREV_REVISION_M $F2_SREV_FPGA $F2_SREV_D2PLUS $F2_SREV_D2PLUS_MS $F2_SREV_CRETE $F2_SREV_CRETE_MS $F2_SREV_CRETE_MS23 $F2_SREV_CRETE_23 $F2_SREV_VERSION_M $F2_SREV_VERSION_CRETE $F2_SREV_VERSION_MAUI_1 $F2_SREV_VERSION_MAUI_2 $F2_EEPROM_ADDR $F2_EEPROM_DATA $F2_EEPROM_CMD $F2_EEPROM_CMD_READ $F2_EEPROM_CMD_WRITE $F2_EEPROM_CMD_RESET $F2_EEPROM_STS $F2_EEPROM_STS_READ_ERROR $F2_EEPROM_STS_READ_COMPLETE $F2_EEPROM_STS_WRITE_ERROR $F2_EEPROM_STS_WRITE_COMPLETE $F2_EEPROM_CFG $F2_EEPROM_CFG_SIZE_M $F2_EEPROM_CFG_SIZE_AUTO $F2_EEPROM_CFG_SIZE_4KBIT $F2_EEPROM_CFG_SIZE_8KBIT $F2_EEPROM_CFG_SIZE_16KBIT $F2_EEPROM_CFG_DIS_WAIT_WRITE_COMPL $F2_EEPROM_CFG_CLOCK_M $F2_EEPROM_CFG_CLOCK_S $F2_EEPROM_CFG_CLOCK_156KHZ $F2_EEPROM_CFG_CLOCK_312KHZ $F2_EEPROM_CFG_CLOCK_625KHZ $F2_EEPROM_CFG_RESV0 $F2_EEPROM_CFG_PROT_KEY_M $F2_EEPROM_CFG_PROT_KEY_S $F2_EEPROM_CFG_EN_L $F2_STA_ID0 $F2_STA_ID1 $F2_STA_ID1_SADH_MASK $F2_STA_ID1_STA_AP $F2_STA_ID1_AD_HOC $F2_STA_ID1_PWR_SAV $F2_STA_ID1_KSRCHDIS $F2_STA_ID1_PCF $F2_STA_ID1_USE_DEFANT $F2_STA_ID1_DEFANT_UPDATE $F2_STA_ID1_RTS_USE_DEF $F2_STA_ID1_ACKCTS_6MB $F2_BSS_ID0 $F2_BSS_ID1 $F2_BSS_ID1_U16_M $F2_BSS_ID1_AID_M $F2_BSS_ID1_AID_S $F2_SLOT_TIME $F2_SLOT_TIME_MASK $F2_TIME_OUT $F2_TIME_OUT_ACK_M $F2_TIME_OUT_CTS_M $F2_TIME_OUT_CTS_S $F2_RSSI_THR $F2_RSSI_THR_MASK $F2_RSSI_THR_BM_THR_M $F2_RSSI_THR_BM_THR_S $F2_USEC $F2_USEC_M $F2_USEC_32_M $F2_USEC_32_S $F2_USEC_TX_LAT_M $F2_USEC_TX_LAT_S $F2_USEC_RX_LAT_M $F2_USEC_RX_LAT_S $F2_BEACON $F2_BEACON_PERIOD_MASK $F2_BEACON_TIM_MASK $F2_BEACON_TIM_S $F2_BEACON_EN $F2_BEACON_RESET_TSF $F2_CFP_PERIOD $F2_TIMER0 $F2_TIMER1 $F2_TIMER2 $F2_TIMER3 $F2_CFP_DUR $F2_RX_FILTER $F2_RX_FILTER_ALL $F2_RX_UCAST $F2_RX_MCAST $F2_RX_BCAST $F2_RX_CONTROL $F2_RX_BEACON $F2_RX_PROM $F2_MCAST_FIL0 $F2_MCAST_FIL1 $F2_DIAG_SW $F2_DIAG_CACHE_ACK $F2_DIAG_ACK_DIS $F2_DIAG_CTS_DIS $F2_DIAG_ENCRYPT_DIS $F2_DIAG_DECRYPT_DIS $F2_DIAG_RX_DIS $F2_DIAG_LOOP_EN $F2_DIAG_CORR_FCS $F2_DIAG_CHAN_INFO $F2_DIAG_EN_SCRAMSD $F2_DIAG_SCRAM_SEED_M $F2_DIAG_SCRAM_SEED_S $F2_DIAG_FRAME_NV0 $F2_DIAG_OBS_PT_SEL_M $F2_DIAG_OBS_PT_SEL_S $F2_TSF_L32 $F2_TSF_U32 $F2_DEF_ANT $F2_LAST_TSTP $F2_NAV $F2_RTS_OK $F2_RTS_FAIL $F2_ACK_FAIL $F2_FCS_FAIL $F2_BEACON_CNT $PHY_BASE $PHY_FRAME_CONTROL $PHY_FC_TURBO_MODE $PHY_FC_TURBO_SHORT $PHY_FRAME_CONTROL1 $PHY_FC_TIMING_ERR $PHY_FC_PARITY_ERR $PHY_FC_ILLRATE_ERR $PHY_FC_ILLLEN_ERR $PHY_FC_SERVICE_ERR $PHY_FC_TX_UNDER_ERR $PHY_CHIP_ID $PHY_ACTIVE $PHY_ACTIVE_EN $PHY_ACTIVE_DIS $PHY_AGC_CONTROL $PHY_AGC_CONTROL_CAL $PHY_AGC_CONTROL_NF $PHY_RX_DELAY $PHY_RX_DELAY_M $PHY_TIMING_CTRL4 $PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M $PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_M $PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S $PHY_TIMING_CTRL4_IQCORR_ENABLE $PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_M $PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S $PHY_TIMING_CTRL4_DO_IQCAL $PHY_IQCAL_RES_PWR_MEAS_I $PHY_IQCAL_RES_PWR_MEAS_Q $PHY_IQCAL_RES_IQ_CORR_MEAS $DEV_AR5211_PCI $DEV_AR5211_PC $DEV_AR5211_AP $DEV_LEGACY $INTERRUPT_F2 $TIMEOUT $ISR_INTERRUPT $DEFAULT_TIMEOUT $DEVLIB_EVENT_ID $COMPARE_PKTS $RECYCLE_RX $RECYCLE_TX $RECYCLE_ALT $TX_STATS $RX_STATS $INTERRUPT_STATS $LAST_FEATURE $ALL_FEATURES $ENABLE_RECYCLE $ENABLE_STATS $RX_NUM_PHY_ERRORS $RX_ALL $RX_GOOD_PACKETS $RX_CRC_ERRORS $RX_DECRYPT_CRC_ERRORS $RX_PHY_ERROR $RX_SIGNAL_STRENGTH $RX_NUM_KNOWN_STATS $RX_DUP_PACKETS $RX_THROUGHPUT $TX_ALL $TX_GOOD_PACKETS $TX_EXCESS_RETRIES $TX_FIFO_UNDERRUN $TX_SHORT_RETRIES $TX_LONG_RETRIES $TX_ACK_SIG_STRENGTH $TX_NUM_BYTES_TX_STATS $DEV_BEANIE_MAUI2_EXPERIMENT $DEV_E2_PCI $DEV_E5_PCI $DEV_E7_PCI $DEV_E7_PCI_PA $DEV_E7_PC_PA $DEV_E9_PCI_PA $DEV_E9_PC_PA $DEV_E9_PC_ANT $DEV_AR5210_PCI $DEV_AR5210_PC $DEV_AR5210_AP $DEV_AR5001 $DEV_AR5001_QMAC $DEV_AR5001_QMAC_FPGA $DEV_11B_FPGA $DEV_OAHU_FPGA $DEV_OAHU_DEF $DEV_OAHU $DEV_OAHU_TEST $DEV_VENICE_FPGA $DEV_VENICE_DEF $DEV_VENICE $DEV_VENICE_DERBY $DEV_HAINAN_SOM $DEV_VENICE_DERBY_2 $DEV_HAINAN_DERBY_2 $DEV_HAINAN_SB_FPGA $DEV_HAINAN_SB_DEF $DEV_HAINAN_DERBY_FPGA $DEV_HAINAN_DERBY_DEF $DEV_GRIFFIN $DEV_EAGLE $DEV_PREDATOR $DEV_PHOENIX $DEV_CONDOR $DEV_DRAGON $MAX_DK_STA_NUM $BUFF_BLOCK_SIZE $COM1_PORT_NUM $COM2_PORT_NUM $COM3_PORT_NUM $COM4_PORT_NUM $SOCK_PORT_NUM $USB_PORT_NUM $MBOX_PORT_NUM $RECV_MBOX $SEND_MBOX $MBOX_BUF_SIZE $READ_BUF_SIZE $WRITE_BUF_SIZE $COM_ERROR_GETHANDLE $COM_ERROR_BUILDDCB $COM_ERROR_CONFIGDEVICE $COM_ERROR_CONFIGBUFFERS $COM_ERROR_SETDTR $COM_ERROR_CLEARDTR $COM_ERROR_PURGEBUFFERS $COM_ERROR_READ $COM_ERROR_WRITE $COM_ERROR_MASK $COM_ERROR_TIMEOUT $COM_ERROR_INVALID_HANDLE $WMAC_FUNCTION $UART_FUNCTION $USB_FUNCTION $SDIO_FUNCTION $MDK_MAX_NUM_DEVICES $UART_FN_DEV_START_NUM $USB_FN_DEV_START_NUM $SDIO_FN_DEV_START_NUM $MAX_CODE_SIZE $MAX_BOOT_DATA_WORDS $MAC_RESET $BB_RESET $BUS_RESET $MODE_11A $MODE_11G $MODE_11B $MODE_11O $HALF_SPEED_MODE $QUARTER_SPEED_MODE $TURBO_ENABLE $LIB_MAX_DEV $MAX_LB_FRAME_LEN $BLOCK_PKT_COUNT $RATE_6 $RATE_9 $RATE_12 $RATE_18 $RATE_24 $RATE_36 $RATE_48 $RATE_54 $RATE_1L $RATE_2L $RATE_2S $RATE_5L $RATE_5S $RATE_11L $RATE_11S $RATE_QUART $RATE_HALF $RATE_1 $RATE_2 $RATE_3 $RATE_GROUP $NUM_RATES $DESC_ANT_A $DESC_ANT_B $USE_DESC_ANT $DESC_CHAIN_2_ANT_A $DESC_CHAIN_2_ANT_B $CONT_DATA $CONT_SINE $CONT_SINGLE_CARRIER $CONT_FRAMED_DATA $DAC_9BIT_MAX_VALUE $DAC_11BIT_MAX_VALUE $ZEROES_PATTERN $ONES_PATTERN $REPEATING_5A $COUNTING_PATTERN $PN7_PATTERN $PN9_PATTERN $REPEATING_10 $RANDOM_PATTERN $NO_REMOTE_STATS $ENABLE_STATS_SEND $ENABLE_STATS_RECEIVE $SKIP_STATS_COLLECTION $SKIP_SOME_STATS $LEAVE_DESC_STATUS $NUM_TO_SKIP_S $NUM_TO_SKIP_M $MDK_NORMAL_PKT $MDK_LAST_PKT $MDK_TX_STATS_PKT $MDK_RX_STATS_PKT $MDK_TXRX_STATS_PKT $MDK_PROBE_PKT $MDK_PROBE_LAST_PKT $MDK_SKIP_STATS_PKT $LAST_DESC_NEXT $LAST_DESC_NULL $LAST_DESC_LOOP $LAST_DESC_FIRST $DESC_INFO_NUM_DESC_MASK $DESC_INFO_NUM_DESC_BIT_START $DESC_INFO_NUM_DESC_WORDS_BIT_START $DESC_INFO_NUM_DESC_WORDS_MASK $DESC_INFO_LAST_DESC_BIT_START $DESC_INFO_LAST_DESC_MASK $DESC_OP_INTR_BIT_START $DESC_OP_INTR_BIT_MASK $DESC_OP_WORD_OFFSET_BIT_START $DESC_OP_WORD_OFFSET_BIT_MASK $DESC_OP_NDESC_OFFSET_BIT_START $DESC_OP_NDESC_OFFSET_BIT_MASK $BUF_ADDR_INC_CLEAR_BUF_BIT_START $BUF_ADDR_INC_CLEAR_BUF_BIT_MASK $PROBE_PKT $TP_SCALE_LOWEST $TP_SCALE_MAX $TP_SCALE_50 $TP_SCALE_25 $TP_SCALE_12 $TP_SCALE_MIN $TP_SCALE_HIGHEST $MAX_MODE $QUARTER_CHANNEL_MASK $CLEAR_QUARTER_CHANNEL_MASK $NUM_TURBO_MASK_PTS $NUM_BASE_MASK_PTS $TMP_LB300 $SPA_E4404B $SPA_E4405B $SPA_8595E $SPA_R3162 $SPA_DET_NEG $SPA_DET_POS $SPA_DET_SAMPLE $SPA_E4404B_MAX_SWEEP_POINTS $SPA_E4405B_MAX_SWEEP_POINTS $SPA_8595E_MAX_SWEEP_POINTS $SPA_R3162_MAX_SWEEP_POINTS $SPA_MAX_SWEEP_POINTS $PM_436A $PM_E4416A $PM_4531 $NRP_Z11 $ATT_11713A $ATT_11713A_110 $PS_E3631A $PS_P6V $PS_P25V $PS_N25V $DEV_0007_CFG $DEV_0010_CFG $DEV_0011_CFG $DEV_F011_CFG $DEV_E011_CFG $DEV_F11B_CFG $DEV_F012_CFG $DEV_0012_CFG $DEV_E012_CFG $DEV_F013_CFG $DEV_0013_CFG $DEV_0014_CFG $DEV_0015_CFG $DEV_0016_CFG $DEV_0017_CFG $DEV_0018_CFG $DEV_0019_CFG $DEV_0020_CFG $DEV_0022_CFG $DEV_00B0_CFG $DEV_00C0_CFG $DEV_FF15_CFG $DEV_F015_CFG $DEV_FF16_CFG $DEV_F016_CFG $pCfgTable $forceSubsystemID $eePromLoad $forceCfgLoad $mode $use_init $beanie2928Mode $refClk $enableXR $loadEar $eepStartLocation $artAniEnable $artAniReuse $chainSelect m_dumpRegs m_changeField m_getFieldForMode m_writeField m_readField m_dumpPciWrites m_enableWep m_enablePAPreDist m_testLib m_displayFieldValues m_getFieldValue m_forcePowerTxMax m_forceSinglePowerTxMax m_forceSinglePcdac m_testChangeChannel m_changeMultipleFieldsAllModes m_changeMultipleFields m_changeCal tram_write_block tram_read_block m_getPcdacForPower m_getMaxPowerForRate m_getPowerIndex m_getArtAniLevel m_setArtAniLevel m_getSwDeviceID m_trigger_sweep m_detect_signal m_set_dev_nums m_force_minccapwr m_config_capture setEepromLoad m_txContFrameBegin mem_read mem_write assign_hw_handle select_hw select_bar reg_read reg_write cfg_read cfg_write mem_alloc mem_free remap_hw create_event wait_on_time mem_write_block dk_quiet wait_on_event mem_read_block isr_feature_enable isr_display_rx_stats isr_display_tx_stats isr_get_all_rx_stats isr_get_all_tx_stats isr_get_rx_stat isr_get_tx_stat isr_log_rx_stats isr_log_tx_stats isr_feature_disable client_close get_dev loadandrun_ihexfile runScreeningTest m_eepromRead m_eepromWrite m_eepromReadBlock m_eepromWriteBlock m_resetDevice m_setResetParams m_checkRegs m_changeChannel m_checkProm m_rereadProm m_txDataSetup m_txDataBegin m_txDataStart m_txDataComplete m_rxDataSetup m_rxDataBegin m_rxDataStart m_rxDataComplete m_txrxDataBegin m_txGetStats m_rxGetStats m_txPrintStats m_rxPrintStats m_rxGetData m_txContBegin m_txContEnd m_setAntenna m_setPowerScale m_setTransmitPower m_setSingleTransmitPower m_devSleep m_closeDevice m_setQueue m_mapQueue m_clearKeyCache ap_reg_read ap_reg_write ap_reg_read16 ap_reg_write16 ap_reg_read8 ap_reg_write8 m_bindDkParamsToDevnum m_gpibSendIFC m_gpibClear m_gpibRSC m_gpibSIC m_gpibRSP m_gpibONL m_gpibRead m_gpibWrite m_gpibQuery m_tempOpen m_tempClose m_tempMeasTemp m_tempSet m_psInit m_psSetOutputState m_psSetVoltage m_psMeasCurrent m_attInit m_attSet m_pmInit m_pmPreset m_pmMeasAvgPower m_pmMeasPeakPower m_spaInit m_spaMeasPhaseNoise m_spaMeasSpectralFlatness m_spaMeasChannelPower m_spaMeasSpectralDensity m_spaMeasOutOfBandEm m_spaMeasPkAvgRatio m_spaMeasFreqDev m_spaMeasTxSpuriousEm m_spaMeasTxSpuriousEmLite m_spaMeasTxPwrDev m_spaMeasRxSpuriousEm m_spaMeasRxSpuriousEmLite m_spaMeasOBW m_spaMeasACP m_spaMeasHarmonics m_spaMeasBandEdge m_spaMeasTelecSpurious m_spaMeasTelecEmission2 m_spaMeasPpsdUnii m_spaMeasPpsdDts m_spaGetModelNo m_spaMeasTxSpurs m_spaMeasEbw m_spaMeasPkPwr m_spaMeasSpectralMask m_spaMeasSpectralMask11b m_spaMeasPHSSpectralMask m_spaMeasRestrictedBand );

# ---------- BASE METHODS -------------

package dk;

sub TIEHASH {
    my ($classname,$obj) = @_;
    return bless $obj, $classname;
}

sub CLEAR { }

sub FIRSTKEY { }

sub NEXTKEY { }

sub FETCH {
    my ($self,$field) = @_;
    my $member_func = "swig_${field}_get";
    $self->$member_func();
}

sub STORE {
    my ($self,$field,$newval) = @_;
    my $member_func = "swig_${field}_set";
    $self->$member_func($newval);
}

sub this {
    my $ptr = shift;
    return tied(%$ptr);
}


# ------- FUNCTION WRAPPERS --------

package dk;

*m_dumpRegs = *dkc::m_dumpRegs;
*m_changeField = *dkc::m_changeField;
*m_getFieldForMode = *dkc::m_getFieldForMode;
*m_writeField = *dkc::m_writeField;
*m_readField = *dkc::m_readField;
*m_dumpPciWrites = *dkc::m_dumpPciWrites;
*m_enableWep = *dkc::m_enableWep;
*m_enablePAPreDist = *dkc::m_enablePAPreDist;
*m_testLib = *dkc::m_testLib;
*m_displayFieldValues = *dkc::m_displayFieldValues;
*m_getFieldValue = *dkc::m_getFieldValue;
*m_forcePowerTxMax = *dkc::m_forcePowerTxMax;
*m_forceSinglePowerTxMax = *dkc::m_forceSinglePowerTxMax;
*m_forceSinglePcdac = *dkc::m_forceSinglePcdac;
*m_testChangeChannel = *dkc::m_testChangeChannel;
*m_changeMultipleFieldsAllModes = *dkc::m_changeMultipleFieldsAllModes;
*m_changeMultipleFields = *dkc::m_changeMultipleFields;
*m_changeCal = *dkc::m_changeCal;
*tram_write_block = *dkc::tram_write_block;
*tram_read_block = *dkc::tram_read_block;
*m_getPcdacForPower = *dkc::m_getPcdacForPower;
*m_getMaxPowerForRate = *dkc::m_getMaxPowerForRate;
*m_getPowerIndex = *dkc::m_getPowerIndex;
*m_getArtAniLevel = *dkc::m_getArtAniLevel;
*m_setArtAniLevel = *dkc::m_setArtAniLevel;
*m_getSwDeviceID = *dkc::m_getSwDeviceID;
*m_trigger_sweep = *dkc::m_trigger_sweep;
*m_detect_signal = *dkc::m_detect_signal;
*m_set_dev_nums = *dkc::m_set_dev_nums;
*m_force_minccapwr = *dkc::m_force_minccapwr;
*m_config_capture = *dkc::m_config_capture;
*setEepromLoad = *dkc::setEepromLoad;
*m_txContFrameBegin = *dkc::m_txContFrameBegin;
*mem_read = *dkc::mem_read;
*mem_write = *dkc::mem_write;
*assign_hw_handle = *dkc::assign_hw_handle;
*select_hw = *dkc::select_hw;
*select_bar = *dkc::select_bar;
*reg_read = *dkc::reg_read;
*reg_write = *dkc::reg_write;
*cfg_read = *dkc::cfg_read;
*cfg_write = *dkc::cfg_write;
*mem_alloc = *dkc::mem_alloc;
*mem_free = *dkc::mem_free;
*remap_hw = *dkc::remap_hw;
*create_event = *dkc::create_event;
*wait_on_time = *dkc::wait_on_time;
*mem_write_block = *dkc::mem_write_block;
*dk_quiet = *dkc::dk_quiet;
*wait_on_event = *dkc::wait_on_event;
*mem_read_block = *dkc::mem_read_block;
*isr_feature_enable = *dkc::isr_feature_enable;
*isr_display_rx_stats = *dkc::isr_display_rx_stats;
*isr_display_tx_stats = *dkc::isr_display_tx_stats;
*isr_get_all_rx_stats = *dkc::isr_get_all_rx_stats;
*isr_get_all_tx_stats = *dkc::isr_get_all_tx_stats;
*isr_get_rx_stat = *dkc::isr_get_rx_stat;
*isr_get_tx_stat = *dkc::isr_get_tx_stat;
*isr_log_rx_stats = *dkc::isr_log_rx_stats;
*isr_log_tx_stats = *dkc::isr_log_tx_stats;
*isr_feature_disable = *dkc::isr_feature_disable;
*client_close = *dkc::client_close;
*get_dev = *dkc::get_dev;
*loadandrun_ihexfile = *dkc::loadandrun_ihexfile;
*runScreeningTest = *dkc::runScreeningTest;
*m_eepromRead = *dkc::m_eepromRead;
*m_eepromWrite = *dkc::m_eepromWrite;
*m_eepromReadBlock = *dkc::m_eepromReadBlock;
*m_eepromWriteBlock = *dkc::m_eepromWriteBlock;
*m_resetDevice = *dkc::m_resetDevice;
*m_setResetParams = *dkc::m_setResetParams;
*m_checkRegs = *dkc::m_checkRegs;
*m_changeChannel = *dkc::m_changeChannel;
*m_checkProm = *dkc::m_checkProm;
*m_rereadProm = *dkc::m_rereadProm;
*m_txDataSetup = *dkc::m_txDataSetup;
*m_txDataBegin = *dkc::m_txDataBegin;
*m_txDataStart = *dkc::m_txDataStart;
*m_txDataComplete = *dkc::m_txDataComplete;
*m_rxDataSetup = *dkc::m_rxDataSetup;
*m_rxDataBegin = *dkc::m_rxDataBegin;
*m_rxDataStart = *dkc::m_rxDataStart;
*m_rxDataComplete = *dkc::m_rxDataComplete;
*m_txrxDataBegin = *dkc::m_txrxDataBegin;
*m_txGetStats = *dkc::m_txGetStats;
*m_rxGetStats = *dkc::m_rxGetStats;
*m_txPrintStats = *dkc::m_txPrintStats;
*m_rxPrintStats = *dkc::m_rxPrintStats;
*m_rxGetData = *dkc::m_rxGetData;
*m_txContBegin = *dkc::m_txContBegin;
*m_txContEnd = *dkc::m_txContEnd;
*m_setAntenna = *dkc::m_setAntenna;
*m_setPowerScale = *dkc::m_setPowerScale;
*m_setTransmitPower = *dkc::m_setTransmitPower;
*m_setSingleTransmitPower = *dkc::m_setSingleTransmitPower;
*m_devSleep = *dkc::m_devSleep;
*m_closeDevice = *dkc::m_closeDevice;
*m_setQueue = *dkc::m_setQueue;
*m_mapQueue = *dkc::m_mapQueue;
*m_clearKeyCache = *dkc::m_clearKeyCache;
*ap_reg_read = *dkc::ap_reg_read;
*ap_reg_write = *dkc::ap_reg_write;
*ap_reg_read16 = *dkc::ap_reg_read16;
*ap_reg_write16 = *dkc::ap_reg_write16;
*ap_reg_read8 = *dkc::ap_reg_read8;
*ap_reg_write8 = *dkc::ap_reg_write8;
*m_bindDkParamsToDevnum = *dkc::m_bindDkParamsToDevnum;
*m_gpibSendIFC = *dkc::m_gpibSendIFC;
*m_gpibClear = *dkc::m_gpibClear;
*m_gpibRSC = *dkc::m_gpibRSC;
*m_gpibSIC = *dkc::m_gpibSIC;
*m_gpibRSP = *dkc::m_gpibRSP;
*m_gpibONL = *dkc::m_gpibONL;
*m_gpibRead = *dkc::m_gpibRead;
*m_gpibWrite = *dkc::m_gpibWrite;
*m_gpibQuery = *dkc::m_gpibQuery;
*m_tempOpen = *dkc::m_tempOpen;
*m_tempClose = *dkc::m_tempClose;
*m_tempMeasTemp = *dkc::m_tempMeasTemp;
*m_tempSet = *dkc::m_tempSet;
*m_psInit = *dkc::m_psInit;
*m_psSetOutputState = *dkc::m_psSetOutputState;
*m_psSetVoltage = *dkc::m_psSetVoltage;
*m_psMeasCurrent = *dkc::m_psMeasCurrent;
*m_attInit = *dkc::m_attInit;
*m_attSet = *dkc::m_attSet;
*m_pmInit = *dkc::m_pmInit;
*m_pmPreset = *dkc::m_pmPreset;
*m_pmMeasAvgPower = *dkc::m_pmMeasAvgPower;
*m_pmMeasPeakPower = *dkc::m_pmMeasPeakPower;
*m_spaInit = *dkc::m_spaInit;
*m_spaMeasPhaseNoise = *dkc::m_spaMeasPhaseNoise;
*m_spaMeasSpectralFlatness = *dkc::m_spaMeasSpectralFlatness;
*m_spaMeasChannelPower = *dkc::m_spaMeasChannelPower;
*m_spaMeasSpectralDensity = *dkc::m_spaMeasSpectralDensity;
*m_spaMeasOutOfBandEm = *dkc::m_spaMeasOutOfBandEm;
*m_spaMeasPkAvgRatio = *dkc::m_spaMeasPkAvgRatio;
*m_spaMeasFreqDev = *dkc::m_spaMeasFreqDev;
*m_spaMeasTxSpuriousEm = *dkc::m_spaMeasTxSpuriousEm;
*m_spaMeasTxSpuriousEmLite = *dkc::m_spaMeasTxSpuriousEmLite;
*m_spaMeasTxPwrDev = *dkc::m_spaMeasTxPwrDev;
*m_spaMeasRxSpuriousEm = *dkc::m_spaMeasRxSpuriousEm;
*m_spaMeasRxSpuriousEmLite = *dkc::m_spaMeasRxSpuriousEmLite;
*m_spaMeasOBW = *dkc::m_spaMeasOBW;
*m_spaMeasACP = *dkc::m_spaMeasACP;
*m_spaMeasHarmonics = *dkc::m_spaMeasHarmonics;
*m_spaMeasBandEdge = *dkc::m_spaMeasBandEdge;
*m_spaMeasTelecSpurious = *dkc::m_spaMeasTelecSpurious;
*m_spaMeasTelecEmission2 = *dkc::m_spaMeasTelecEmission2;
*m_spaMeasPpsdUnii = *dkc::m_spaMeasPpsdUnii;
*m_spaMeasPpsdDts = *dkc::m_spaMeasPpsdDts;
*m_spaGetModelNo = *dkc::m_spaGetModelNo;
*m_spaMeasTxSpurs = *dkc::m_spaMeasTxSpurs;
*m_spaMeasEbw = *dkc::m_spaMeasEbw;
*m_spaMeasPkPwr = *dkc::m_spaMeasPkPwr;
*m_spaMeasSpectralMask = *dkc::m_spaMeasSpectralMask;
*m_spaMeasSpectralMask11b = *dkc::m_spaMeasSpectralMask11b;
*m_spaMeasPHSSpectralMask = *dkc::m_spaMeasPHSSpectralMask;
*m_spaMeasRestrictedBand = *dkc::m_spaMeasRestrictedBand;

# ------- VARIABLE STUBS --------

package dk;

*F2_CR = *dkc::F2_CR;
*F2_CR_RXE = *dkc::F2_CR_RXE;
*F2_CR_RXD = *dkc::F2_CR_RXD;
*F2_CR_SWI = *dkc::F2_CR_SWI;
*F2_RXDP = *dkc::F2_RXDP;
*F2_CFG = *dkc::F2_CFG;
*F2_CFG_SWTD = *dkc::F2_CFG_SWTD;
*F2_CFG_SWTB = *dkc::F2_CFG_SWTB;
*F2_CFG_SWRD = *dkc::F2_CFG_SWRD;
*F2_CFG_SWRB = *dkc::F2_CFG_SWRB;
*F2_CFG_SWRG = *dkc::F2_CFG_SWRG;