atheros-eep.txt

Atheros AP Test with Agilent N4010A source code

;Atheros Reference Card EEPROM contents
;Version 2.1 7/29/2002
;-------------------------------------------------------------------------------
;REVISION HISTORY
;-------------------------------------------------------------------------------
;Ver  Revision History							            Date
;
;1.00 Initial Relase of Tuples                                      	10/12/00
;1.01 Small fixes to tuples. Inusre 1MB for F2 Proto's using 1MB.       10/16/00
;1.02 Changed name of file, updated CISTPL_BAR to reflect 64KB for D2+.	12/12/00
;1.03 Changed CISTPL_VERS1 from Card Access information to Atheos info.	12/22/00
;1.04 Updated CISTPL_VERS1 with Atheros PN info: AR5BCB-01-01           01/15/01
;1.05 Reformatted the VENDOR SPECIFIC comment banner to work            01/29/01
;	with eepnumfix.pl. Fixed PN to AR5BCB-01-01.
;1.06 Fix the Link Tuple on CISTPL_VERS1 to take into account the added	02/05/01
;	-01-01.
;1.07 Above edit only fixed the comment.  Fixed the LINK Tuple data.    02/07/01
;1.08 Changed the PMData_D0 and PMData_D3 to C606 = D0=1.98W, D3=.06W.	03/09/01
;1.09 Added write protect at 0x3f.                                      03/22/01
;1.10 Fixed write protect value: 0x0005 = Write Only /No Read,          04/04/01
;	0x000A = Read Only / No Write.
;1.11 Added 'EERPOM_MAGIC' value to 0x3D, Added comments for            04/11/01
;	MAC words 0-2.
;1.12 Added Static and Avg current to CISTPL_CFTABLE_CB.                04/16/01
;1.13 Added reserved area for Atheros initialization info E0-FF         05/08/01
;1.14 Zeroed protect bits and added MIN_GNT/MAX_LAT                     05/30/01
;1.15 Added offset 0x0F Clkrunen (1 = Enable, 0=disabled) in Sleep Mode 06/01/01
;1.16 Updated Atheros PN and PCMCIA Revision to 7.1.                    07/09/01
;	Added Subsys ID's 168c and 0007
;1.17 Documented last 128B with the new EEPROM setup information        07/30/01
;1.18 Set location 0x3E to 0001 to protect key cache from SW read       08/10/01
;1.19 Added Vendor Data area in EEPROM in locations B0-BE               08/16/01
;1.20 Changed comments to reflect data sheet names                      08/21/01
;1.21 Rechanged version back to 01-01 for PCMCIA compatibility          08/28/01
;2.0  Added description to 0xf for RF_SILIENT				07/18/02
;2.1  DeviceID = 0x0012, SSID=0x0000, fixed the 6th tuple, DeviceID
;     reflected correctly in 2nd tuple.					07/29/02
;
;-------------------------------------------------------------------------------
;DESCRIPTION OF FORMAT:
;-------------------------------------------------------------------------------
;EEPROM has 256 locations with 16 bits per location
;
;for CONFIGURATION...
;double byte per line for now
;bytes are in 'readable' order
;the parser will swap the bytes for programming into the EEPROM (little-endian)
;
;for TUPLES ...
;single byte per line - single byte easier to read, & mk notes
;bytes are in the same order as one would expect to see tuples in
;the parser swaps the bytes for burning into the EEPROM
;the 'above' byte goes into bits 7-0 and the 'below' byte goes into bits 15-8
;so a
;13
;03
;would go into the EEPROM as 0313
;ascii-text version of the hex numbers w/o 0x before or h after
;the 0 or F fill lines after tuples (if tpl don't use space) are dbl byte/line
;
;for VENDOR SPECIFIC DATA
;double byte per line for now
;bytes are in 'readable' order
;the parser will swap the bytes for programming into the EEPROM (little-endian)
;
;PCI configuration data first in 00-3F locations (64 WORDS)
;CIS information next in 40-BE locations (112 WORDS)
;VENDOR OEM information next in B0-BE locations (15 WORDS)
;Device specific information next in BF-FF locations (65 WORDS)
;ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
;PCI CONFIGURATION LOCATIONS 00-3F
;ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
0012	;00;    Device_ID
168C	;01;    Vendor_ID
0200	;02;    Class Code (24 b) 23:8 of code -> 15:0 of word
0001	;03;    Class Code         7:0 of code -> 15:8 of word, Revision ID -> 7:0
0000	;04;    
5001	;05;    CIS_PTR (total of 32 bits) [15:0] (the lower 16 bits here)
0000	;06;    CIS_PTR                    [31:16](the upper 16 bits here)
0000	;07;    SSYS_ID (Subsystem ID)
168C	;08;    SSYS_VEND_ID (Subsystem Vendor ID)
1C0A	;09;    MAX_LAT [15:8], MIN_GNT [7:0]
0100	;0a;    INT_PIN [15:8], 0'S [7:0]
0000	;0b;    Reserved
0002	;0c;    PM_CAP (Power Management Capabilities)
0002	;0d;    0'S [15:2], PM_DATA_SCALE [1:0] 
C606	;0e;    PM_DATA_D0 [15:8], PM_DATA_D3 [7:0]:C606 = 1.98W in D0, .06W in D3
0001	;0f;    CLKRUN_ENABLE[0], (Enable = 1, Disable = 0), RFSILENT_POLARITY[1], RFSILENT_GPIO_SEL[4:2]
0000	;10;    RESERVED 
0000	;11;    RESERVED 
0000	;12;    RESERVED 
0000	;13;    RESERVED 
0000	;14;    RESERVED 
0000	;15;    RESERVED 
0000	;16;    RESERVED 
0000	;17;    RESERVED 
0000	;18;    RESERVED 
0000	;19;    RESERVED 
0000	;1a;    RESERVED 
0000	;1b;    RESERVED 
0000	;1c;    RESERVED 
0000	;1d;    MAC Address LSW (15:0) 
0000	;1e;    MAC Address (31:16) 
0000	;1f;    MAC Address MSW (47:32)
0000	;20;    RESERVED
0000	;21;    RESERVED
0000	;22;    RESERVED
0000	;23;    RESERVED
0000	;24;    RESERVED
0000	;25;    RESERVED
0000	;26;    RESERVED
0000	;27;    RESERVED
0000	;28;    RESERVED 
0000	;29;    RESERVED 
0000	;2a;    RESERVED 
0000	;2b;    RESERVED 
0000	;2c;    RESERVED 
0000	;2d;    RESERVED 
0000	;2e;    RESERVED 
0000	;2f;    RESERVED 
0000	;30;    RESERVED 
0000	;31;    RESERVED 
0000	;32;    RESERVED 
0000	;33;    RESERVED 
0000	;34;    RESERVED 
0000	;35;    RESERVED 
0000	;36;    RESERVED 
0000	;37;    RESERVED 
0000	;38;    RESERVED 
0000	;39;    RESERVED 
0000	;3a;    RESERVED 
0000	;3b;    RESERVED 
0000	;3c;    RESERVED 
5AA5	;3d;    EEPROM_MAGIC Word 
0000	;3e;    KEY_TABLE_RD_PROTECT [0]
0000	;3f;    EEPROM Protection [15:0]. 0x0A write protects location 0 - 0x3F.

;ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
;CIS LOCATIONS 40-AF
;ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
;32-bit memory with even word in lower 16 bits and odd word in upper 16 bits
;this space does not correspond to the PCI configuration space
;
;1st tuple
13	;40;    13=LINKTARGET [3.1.4]
03	;40;    03=Link to next tuple chain
43	;41;    "C"
49	;41;    "I"
53	;42;    "S"

;2nd tuple
20	;42;    20=MANFID, Manufacturer ID tuple [3.2.9]
04	;43;    04=Link to next tuple chain
71	;43;   
02	;44;    0271=Atheros manufacturing code
12	;44;   
00	;45;    0007=Atheros Device ID for AR5001

;3rd tuple
04	;45;    04=CONFIG_CB, configuration for a cardbus card [3.3.5]
06	;46;    06=Link to next tuple chain
03	;46;    size of fields - must be 3 to represent 4 bytes per field
01	;47;    indx # of last entry in card config table -> see 4th tuple below
00	;47;   
00	;48;   
00	;48;   
00	;49;    address of 0000 0000 because we don't have any status registers

;4th tuple
05	;49;    05=CFTABLE_ENTRY_CB, config table entry for cardbus card [3.3.3]
0E	;4a;    0E=Link to next tuple chain
41	;4a;    bit 6 set = the default config; 01=last entry in config table
B1	;4b;    b1:0 = 01 = VCC power description only
	;    b3 = 0 for no I/O space description
	;    b4 = 1 for interrupt structure description
	;    b5 = 1 for memory space description
	;    b7 = 1 for a miscellaneous field structure
39	;4b;    b0 = 1 for nominal operating voltage
	;      b3 = 1 for static current
	;      b4 = 1 for average current
	;      b5 = 1 for peak current
B5	;4c;    b6:3=mant=0110=6->3 b2:0=exp=101=5->1V range -> 3V for VCC power
1E	;4c;    1E hex = 30 decimal, goes to rt of above value, so total VCC = 3.3
2D	;4d;    b6:3=mant=0101=5->2.5 b2:0=exp=101=4=10ma Static Current = 25ma for 3.3V  
4E	;4d;    b6:3=mant=1001=9->4.5 b2:0=exp=110=6=100mA Avg Current = 450ma.  	
56	;4e;    b6:3=mant=1010=A->5 b2:0=exp=110=6=100mA Avg Current = 500ma.  	
30	;4e;    b7=0 for NO INTERRUPT SHARING among several cards
	;      b6=0 for no pulse interrupts
	;      b5=1 for level interrupts
	;      b4=1 for linking the int to any int shown by the following 2 bytes
FF	;4f;    interrupts 7-0
FF	;4f;    interrupts 15-8
02	;50;    b1=1 for first BAR to use for memory
E9	;50;    b7=1 for there is one more byte -> required by METAFORMAT.
	;    b6=1 for fast back-to-back supported
	;    b5=1 for SERR# supported
	;    b4=0 for no wait cycle control supported
	;    b3=1 for Parity error response
	;    b2=0 for no VGA palette snoop
	;    b1=0 for no memory write & invalidate
	;    b0=1 for Bus Master
00	;51;    no wake up events 

;5th tuple
07	;51;    07=CISTPL_BAR Base address register [3.3.1]
06	;52;    06=Link to next tuple
01	;52;    01 = BAR1, mem space, no prefetch, no cache, no mapping restriction
00	;53;    RESERVED - must be 0
00	;53;    Base Address Register Size - 4 bytes altogether 
00	;54;    Size in Bytes of the memory space the BAR is mapped to
01	;54;    Card has 64KB memory space -> 2^16 = 64KB
00	;55;    0001 0000 = 65,536 of memory

;6th tuple
15	;55;    15=CISTPL_VERS_1 Level 1 version and product informatoin [3.2.10]
52	;56;    50=Link to next tuple
07	;56;    07=major version 7
01	;57;    01=minor version 1 -> both bytes together mean version 7.1
41   ;57;   A
74   ;58;   t
68   ;58;   h
65   ;59;   e
72   ;59;   r
6f   ;5a;   o
73   ;5a;   s
20   ;5b;   <space>
43   ;5b;   C
6f   ;5c;   o
6d   ;5c;   m
6d   ;5d;   m
75   ;5d;   u
6e   ;5e;   n
69   ;5e;   i
63   ;5f;   c
61   ;5f;   a
74   ;60;   t
69   ;60;   i
6f   ;61;   o
6e   ;61;   n
73   ;62;   s
2c   ;62;   ,
20   ;63;   <space>
49   ;63;   I
6e   ;64;   n
63   ;64;   c
2e   ;65;   .
00   ;65;   <null>
41   ;66;   A
52   ;66;   R
35   ;67;   5
30   ;67;   0
30   ;68;   0
31   ;68;   1
2d   ;69;   -
30   ;69;   0
30   ;6a;   0
30   ;6a;   0
30   ;6b;   0