📄 mconfig.c
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}
// phyonly reset. Used in the emulation board
#if defined(SPIRIT_AP) || defined(FREEDOM_AP)
#ifdef EMULATION
REGW(devNum,0x9928,0);
mSleep(10);
REGW(devNum,0x9928,1);
#endif
#endif
#ifdef FREEDOM_AP
// changeField(devNum, "rf_ovr", 1);
// changeField(devNum, "rf_gain_I", 0x10);
#endif
// Setup Values from EEPROM - only touches EEPROM the first time
//FJC: 06/09/03 moved reading eeprom to here, since it reads the EAR
if (pLibDev->eePromLoad) {
if(pLibDev->swDevID >= 0x0012) {
REGW(devNum, 0x6010, REGR(devNum, 0x6010) | 0x3);
}
if(!setupEEPromMap(devNum)) {
mError(devNum, EIO, "Error: unable to load EEPROM\n");
return;
}
if((((pLibDev->eepData.version >> 12) & 0xF) >= 4) &&
(((pLibDev->eepData.version >> 12) & 0xF) <= 5) &&
(!isFalcon(devNum)))
{
earHere = ar5212IsEarEngaged(devNum, pLibDev->pEarHead, freq);
// printf("In reset Device pLibDev->p16kEepHeader->majorVersion loadcfgdata ar5212IsEarEngaged\n");
}
}
//do a check for EAR changes to rf registers
if ((earHere) && (!isFalcon(devNum))){
ar5212EarModify(devNum, pLibDev->pEarHead, EAR_LC_RF_WRITE, freq, &modifier);
}
/* Initialize chips with values from register file */
for(i = 0; i < pLibDev->sizePciValuesArray; i++ ) {
#if defined(SPIRIT_AP) || defined(FREEDOM_AP)
#ifdef EMULATION
if (pLibDev->pciValuesArray[i].offset == 0x9928) continue;
#endif
#endif
/*if dealing with a version 2 config file,
then all values are found in the base array */
pciValues[i].offset = pLibDev->pciValuesArray[i].offset;
if((pLibDev->turbo == TURBO_ENABLE) && (ar5kInitData[pLibDev->ar5kInitIndex].cfgVersion < 2)) {
if (pLibDev->devMap.remoteLib) {
pciValues[i].baseValue = pLibDev->pciValuesArray[i].turboValue;
}
else {
#if defined(COBRA_AP)
if(pLibDev->pciValuesArray[i].offset < 0x14000)
#endif
REGW(devNum, pLibDev->pciValuesArray[i].offset, pLibDev->pciValuesArray[i].turboValue);
}
}
else {
if (pLibDev->devMap.remoteLib) {
pciValues[i].baseValue = pLibDev->pciValuesArray[i].baseValue;
}
else {
#if defined(COBRA_AP)
if(pLibDev->pciValuesArray[i].offset < 0x14000)
#endif
REGW(devNum, pLibDev->pciValuesArray[i].offset, pLibDev->pciValuesArray[i].baseValue);
}
}
//++JC++ For Griffin bank6 problem - temporary - remove after the problem is fixed
// Capture the data that is written to bank6
if((pLibDev->swDevID & 0xff) == 0x0018) {
if (isGriffin_1_0(pLibDev->macRev) || isGriffin_1_1(pLibDev->macRev)) {
if((pLibDev->pciValuesArray[i].offset == 0x989c) || (pLibDev->pciValuesArray[i].offset == 0x98d8)) {
if ((pLibDev->pciValuesArray[i].offset == 0x989c) && (bank6_over == 0)) {
bank6_data[zz] = pLibDev->pciValuesArray[i].baseValue;
zz++;
} else if ((pLibDev->pciValuesArray[i].offset == 0x98d8) && (zz >= 25)) {
bank6_data[zz] = pLibDev->pciValuesArray[i].baseValue;
bank6_over = 1;
}
}
}
}
//++JC++
} // end of for
if (pLibDev->devMap.remoteLib)
sendPciWrites(devNum, pciValues, pLibDev->sizePciValuesArray);
//++JC++
// Form the data that needs to be compared with data read out of bank6
if(isGriffin(pLibDev->swDevID)) {
if (isGriffin_1_0(pLibDev->macRev) || isGriffin_1_1(pLibDev->macRev)) {
di_31_00 = (bank6_data[zz - 8] & 0xff) | ((bank6_data[zz - 7] & 0xff) << 8) |
((bank6_data[zz - 6] & 0xff) << 16) | ((bank6_data[zz - 5] & 0xff) << 24);
di_63_32 = (bank6_data[zz - 4] & 0xff) | ((bank6_data[zz - 3] & 0xff) << 8) |
((bank6_data[zz - 2] & 0xff) << 16) | ((bank6_data[zz - 1] & 0xff) << 24);
di_67_64 = (bank6_data[zz] & 0xf);
// Program reg5 to read out tx chain
REGW(devNum, (0x9800+(0x34<<2)), 0x0);
os1 = 1;
os0 = 0;
dreg1 = 0;
dreg0 = 0;
da2 = 1;
da1 = 1;
da0 = 0;
tmp = da0<<20 | da1<<19 | da2<<18 | dreg0<<17 | dreg1<<16
| 0x5<<2 | os0<<1 | os1;
REGW(devNum, (0x9800+(0x34<<2)), tmp);
//------------------------------------------------------------------------
//loop to do write and check
//------------------------------------------------------------------------
shift_good = 0;
num_tries = 0;
while ((shift_good == 0) && (num_tries<1000)) {
//
// shift in data
//
for (kk=0;kk<27;kk++) {
if (kk==26) {
offset = 0x36;
} else {
offset = 0x27;
}
data = bank6_data[zz-26+kk];
REGW(devNum,0x9800+(offset<<2), data);
}
//
// shift out data
//
for (kk=0; kk<32; kk++) {
REGW(devNum,(0x9800+(0x20<<2)), 0x00010000);
}
do_31_00 = REGR(devNum,0x9800+(256<<2));
for (kk=0; kk<32; kk++) {
REGW(devNum,(0x9800+(0x20<<2)), 0x00010000);
}
do_63_32 = REGR(devNum,0x9800+(256<<2));
for (kk=0; kk<4; kk++) {
REGW(devNum,(0x9800+(0x20<<2)), 0x00010000);
}
do_67_64 = (REGR(devNum,0x9800+(256<<2)))>>28;
//printf ("\n");
//printf (" di: 0x%01x 0x%08x 0x%08x\n", di_67_64, di_63_32, di_31_00);
//printf (" do: 0x%01x 0x%08x 0x%08x\n", do_67_64, do_63_32, do_31_00);
if ((((di_31_00)&0xffffffff) != ((do_31_00)&0xffffffff))
|| (((di_63_32)&0xffffffff) != ((do_63_32)&0xffffffff))
|| ((di_67_64 & 0xf) != (do_67_64 & 0xf))) {
//printf ("\n");
//printf (" di: 0x%01x 0x%08x 0x%08x\n", di_67_64, di_63_32, di_31_00);
//printf (" do: 0x%01x 0x%08x 0x%08x\n", do_67_64, do_63_32, do_31_00);
shift_good = 0;
} else {
shift_good = 1;
}
num_tries++;
}
//printf ("Done Bank 6 problem workaround\n\n");
}
}
// End of workaround for griffin bank6 problem
//++JC++
if((turbo == TURBO_ENABLE) && (ar5kInitData[pLibDev->ar5kInitIndex].cfgVersion < 3)) {
//quick enable to venice 11g turbo. Force minimum fields in here
//version 3 config files have a 11g turbo column
if(((pLibDev->swDevID & 0xff) >= 0x0013) && ((pLibDev->mode == MODE_11G)||(pLibDev->mode == MODE_11O))) {
changeRegValueField(devNum, "bb_short20", 1);
changeRegValueField(devNum, "rf_turbo", 1);
changeRegValueField(devNum, "bb_turbo", 1);
changeRegValueField(devNum, "mc_turbo_mode", 1);
changeRegValueField(devNum, "bb_dyn_ofdm_cck_mode", 0);
changeRegValueField(devNum, "bb_agc_settling", 0x25);
changeRegValueField(devNum, "mc_sifs_dcu", 480);
changeRegValueField(devNum, "mc_slot_dcu", 480);
changeRegValueField(devNum, "mc_eifs_dcu", 4480);
changeRegValueField(devNum, "mc_usec_duration", 80);
changeRegValueField(devNum, "mc_sifs_duration_usec", 6);
changeRegValueField(devNum, "mc_cts_timeout", 0x12c0);
changeRegValueField(devNum, "mc_ack_timeout", 0x12c0);
changeRegValueField(devNum, "mc_usec", 79);
}
}
if(((pLibDev->swDevID & 0xff) >= 0x0013) && (pLibDev->mode == MODE_11O)) {
changeRegValueField(devNum, "bb_dyn_ofdm_cck_mode", 0);
}
/* Remove this after moving this value to config file */
#ifdef FREEDOM_AP
/*
REGW(devNum,0x9848,0x0018d410);
REGW(devNum,0x996c, 0x1301); // sigma-delta control
REGW(devNum, 0x982c, 0x0002effe);
*/
#endif
/* delta_slope_coeff_exp and delta_slope_coeff_man for venice */
if ((pLibDev->swDevID & 0x00ff) >= 0x0013) {
double fclk,coeff;
A_UINT32 coeffExp,coeffMan;
A_UINT32 deltaSlopeCoeffMan, deltaSlopeCoeffExp;
A_UINT32 progCoeff;
switch (pLibDev->mode) {
case MODE_11A:
if(pLibDev->swDevID == 0xf013) {
fclk = 16.0;
}
else {
switch (turbo) {
case QUARTER_SPEED_MODE:
fclk = 10;
if(isEagle(pLibDev->swDevID)) {
writeField(devNum, "bb_quarter_rate_mode", 1);
writeField(devNum, "bb_half_rate_mode", 0);
writeField(devNum, "bb_window_length", 3);
}
break;
case HALF_SPEED_MODE:
fclk = 20;
if(isEagle(pLibDev->swDevID)) {
writeField(devNum, "bb_quarter_rate_mode", 0);
writeField(devNum, "bb_half_rate_mode", 1);
writeField(devNum, "bb_window_length", 3);
}
break;
case TURBO_ENABLE:
fclk = 80;
if(isEagle(pLibDev->swDevID)) {
writeField(devNum, "bb_quarter_rate_mode", 0);
writeField(devNum, "bb_half_rate_mode", 0);
writeField(devNum, "bb_window_length", 0);
}
break;
default : // base
fclk = 40;
if(isEagle(pLibDev->swDevID)) {
writeField(devNum, "bb_quarter_rate_mode", 0);
writeField(devNum, "bb_half_rate_mode", 0);
writeField(devNum, "bb_window_length", 0);
}
break;
}
}
progCoeff = 1;
break;
case MODE_11G:
case MODE_11O:
if(pLibDev->swDevID == 0xf013) {
fclk = (16.0 * 10.0) / 11.0;
}
else {
switch (turbo) {
case QUARTER_SPEED_MODE:
fclk = 10;
if(isEagle(pLibDev->swDevID)) {
writeField(devNum, "bb_quarter_rate_mode", 1);
writeField(devNum, "bb_half_rate_mode", 0);
}
break;
case HALF_SPEED_MODE:
fclk = 20;
if(isEagle(pLibDev->swDevID)) {
writeField(devNum, "bb_quarter_rate_mode", 0);
writeField(devNum, "bb_half_rate_mode", 1);
}
break;
case TURBO_ENABLE:
fclk = 80;
if(isEagle(pLibDev->swDevID)) {
writeField(devNum, "bb_quarter_rate_mode", 0);
writeField(devNum, "bb_half_rate_mode", 0);
}
break;
default : // base
fclk = 40;
if(isEagle(pLibDev->swDevID)) {
writeField(devNum, "bb_quarter_rate_mode", 0);
writeField(devNum, "bb_half_rate_mode", 0);
}
break;
}
}
progCoeff = 1;
break;
default:
fclk = 0;
progCoeff = 0;
break;
}
if (progCoeff) {
coeff = (2.5 * fclk) / ((double)freq);
coeffExp = 14 - (int)(floor(log10(coeff)/log10(2)));
coeffMan = (int)(floor((coeff*(pow(2,coeffExp))) + 0.5));
deltaSlopeCoeffExp = coeffExp - 16;
deltaSlopeCoeffMan = coeffMan;
REGW(devNum, 0x9814, (REGR(devNum,0x9814) & 0x00001fff) |
(deltaSlopeCoeffExp << 13) |
(deltaSlopeCoeffMan << 17));
}
}
//Disable all the mac queue clocks
if((pLibDev->swDevID != 0x0007) && (pLibDev->swDevID != 0x0010)) {
disable5211QueueClocks(devNum);
}
// Byteswap Tx and Rx descriptors for Big Endian systems
#if defined(ARCH_BIG_ENDIAN)
REGW(devNum, F2_CFG, F2_CFG_SWTD | F2_CFG_SWRD);
#endif
#ifdef HEADER_LOAD_SCHEME
else if (pLibDev->eePromHeaderLoad) {
setupEEPromHeaderMap(devNum);
}
#endif //HEADER_LOAD_SCHEME
// Setup the macAddr in the chip
memcpy(pLibDev->macAddr.octets, mac, WLAN_MAC_ADDR_SIZE);
#ifndef ARCH_BIG_ENDIAN
REGW(devNum, F2_STA_ID0, pLibDev->macAddr.st.word);
temp1 = REGR(devNum, F2_STA_ID1);
temp2 = (temp1 & 0xffff0000) | F2_STA_ID1_AD_HOC | pLibDev->macAddr.st.half | F2_STA_ID1_DESC_ANT;
REGW(devNum, F2_STA_ID1, temp2);
#else
{
A_UINT32 addr;
addr = swap_l(pLibDev->macAddr.st.word);
REGW(devNum, F2_STA_ID0, addr);
addr = (A_UINT32)swap_s(pLibDev->macAddr.st.half);
REGW(devNum, F2_STA_ID1, (REGR(devNum, F2_STA_ID1) & 0xffff0000⌨️ 快捷键说明
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