ar5211reg.h

Atheros AP Test with Agilent N4010A source code

#define F2_EEPROM_CMD_READ	 0x00000001
#define F2_EEPROM_CMD_WRITE	 0x00000002
#define F2_EEPROM_CMD_RESET	 0x00000004

#define F2_EEPROM_STS	    0x600c  // EEPROM status register
#define F2_EEPROM_STS_READ_ERROR	 0x00000001
#define F2_EEPROM_STS_READ_COMPLETE	 0x00000002
#define F2_EEPROM_STS_WRITE_ERROR	 0x00000004
#define F2_EEPROM_STS_WRITE_COMPLETE 0x00000008

#define F2_EEPROM_CFG	    0x6010  // EEPROM configuration register
#define F2_EEPROM_CFG_SIZE_M	 0x00000003 // Mask for EEPROM size determination override
#define F2_EEPROM_CFG_SIZE_AUTO		0
#define F2_EEPROM_CFG_SIZE_4KBIT	1
#define F2_EEPROM_CFG_SIZE_8KBIT	2
#define F2_EEPROM_CFG_SIZE_16KBIT	3
#define F2_EEPROM_CFG_DIS_WAIT_WRITE_COMPL 0x00000004 // Disable wait for write completion
#define F2_EEPROM_CFG_CLOCK_M	 0x00000018 // Mask for EEPROM clock rate control
#define F2_EEPROM_CFG_CLOCK_S	 3			// Shift for EEPROM clock rate control
#define F2_EEPROM_CFG_CLOCK_156KHZ	0
#define F2_EEPROM_CFG_CLOCK_312KHZ	1
#define F2_EEPROM_CFG_CLOCK_625KHZ	2
#define F2_EEPROM_CFG_RESV0		 0x000000E0 // Reserved
#define F2_EEPROM_CFG_PROT_KEY_M 0x00FFFF00 // Mask for EEPROM protection key
#define F2_EEPROM_CFG_PROT_KEY_S 8			// Shift for EEPROM protection key
#define F2_EEPROM_CFG_EN_L		 0x01000000 // EPRM_EN_L setting

// MAC PCU Registers
#define F2_STA_ID0          0x8000  // MAC station ID0 register - low 32 bits
#define F2_STA_ID1          0x8004  // MAC station ID1 register - upper 16 bits
#define F2_STA_ID1_SADH_MASK   0x0000FFFF // Mask for upper 16 bits of MAC addr
#define F2_STA_ID1_STA_AP      0x00010000 // Device is AP
#define F2_STA_ID1_AD_HOC      0x00020000 // Device is ad-hoc
#define F2_STA_ID1_PWR_SAV     0x00040000 // Power save reporting in self-generated frames
#define F2_STA_ID1_KSRCHDIS    0x00080000 // Key search disable
#define F2_STA_ID1_PCF		   0x00100000 // Observe PCF
#define F2_STA_ID1_USE_DEFANT  0x00200000 // Use default antenna
#define F2_STA_ID1_DEFANT_UPDATE 0x00400000 // Update default antenna w/ TX antenna
#define F2_STA_ID1_RTS_USE_DEF   0x00800000 // Use default antenna to send RTS
#define F2_STA_ID1_ACKCTS_6MB  0x01000000 // Use 6Mb/s rate for ACK & CTS

#define F2_BSS_ID0          0x8008  // MAC BSSID low 32 bits
#define F2_BSS_ID1          0x800C  // MAC BSSID upper 16 bits / AID
#define F2_BSS_ID1_U16_M     0x0000FFFF // Mask for upper 16 bits of BSSID
#define F2_BSS_ID1_AID_M     0xFFFF0000 // Mask for association ID 
#define F2_BSS_ID1_AID_S     16         // Shift for association ID 

#define F2_SLOT_TIME        0x8010  // MAC Time-out after a collision
#define F2_SLOT_TIME_MASK    0x000007FF // Slot time mask

#define F2_TIME_OUT         0x8014  // MAC ACK & CTS time-out
#define F2_TIME_OUT_ACK_M    0x00001FFF // Mask for ACK time-out
#define F2_TIME_OUT_CTS_M    0x1FFF0000 // Mask for CTS time-out
#define F2_TIME_OUT_CTS_S    16         // Shift for CTS time-out

#define F2_RSSI_THR         0x8018  // MAC Beacon RSSI warning and missed beacon threshold
#define F2_RSSI_THR_MASK     0x000000FF // Mask for Beacon RSSI warning threshold
#define F2_RSSI_THR_BM_THR_M 0x0000FF00 // Mask for Missed beacon threshold
#define F2_RSSI_THR_BM_THR_S 8          // Shift for Missed beacon threshold

#define F2_USEC             0x801c  // MAC transmit latency register
#define F2_USEC_M            0x0000007F // Mask for clock cycles in 1 usec
#define F2_USEC_32_M         0x00003F80 // Mask for number of 32MHz clock cycles in 1 usec
#define F2_USEC_32_S         7          // Shift for number of 32MHz clock cycles in 1 usec
#define F2_USEC_TX_LAT_M     0x000FC000 // Mask for tx latency to start of SIGNAL (usec)
#define F2_USEC_TX_LAT_S     14         // Shift for tx latency to start of SIGNAL (usec)
#define F2_USEC_RX_LAT_M     0x03F00000 // Mask for rx latency to start of SIGNAL (usec)
#define F2_USEC_RX_LAT_S     20         // Shift for rx latency to start of SIGNAL (usec)

#define F2_BEACON           0x8020  // MAC beacon control value/mode bits
#define F2_BEACON_PERIOD_MASK 0x0000FFFF  // Beacon period mask in TU/msec
#define F2_BEACON_TIM_MASK    0x007F0000  // Mask for byte offset of TIM start
#define F2_BEACON_TIM_S       16          // Shift for byte offset of TIM start
#define F2_BEACON_EN          0x00800000  // beacon enable
#define F2_BEACON_RESET_TSF   0x01000000  // Clears TSF to 0

#define F2_CFP_PERIOD       0x8024  // MAC CFP Interval (TU/msec)
#define F2_TIMER0           0x8028  // MAC Next beacon time (TU/msec)
#define F2_TIMER1           0x802c  // MAC DMA beacon alert time (1/8 TU)
#define F2_TIMER2           0x8030  // MAC Software beacon alert (1/8 TU)
#define F2_TIMER3           0x8034  // MAC ATIM window time

#define F2_CFP_DUR          0x8038  // MAC maximum CFP duration in TU

#define F2_RX_FILTER        0x803C  // MAC receive filter register
#define F2_RX_FILTER_ALL     0x00000000 // Disallow all frames
#define F2_RX_UCAST          0x00000001 // Allow unicast frames
#define F2_RX_MCAST          0x00000002 // Allow multicast frames
#define F2_RX_BCAST          0x00000004 // Allow broadcast frames
#define F2_RX_CONTROL        0x00000008 // Allow control frames
#define F2_RX_BEACON         0x00000010 // Allow beacon frames
#define F2_RX_PROM           0x00000020 // Promiscuous mode, all packets

#define F2_MCAST_FIL0       0x8040  // MAC multicast filter lower 32 bits
#define F2_MCAST_FIL1       0x8044  // MAC multicast filter upper 32 bits

#define F2_DIAG_SW          0x8048  // MAC PCU control register
#define F2_DIAG_CACHE_ACK    0x00000001 // disable ACK when no valid key found
#define F2_DIAG_ACK_DIS      0x00000002 // disable ACK generation
#define F2_DIAG_CTS_DIS      0x00000004 // disable CTS generation
#define F2_DIAG_ENCRYPT_DIS  0x00000008 // disable encryption
#define F2_DIAG_DECRYPT_DIS  0x00000010 // disable decryption
#define F2_DIAG_RX_DIS       0x00000020 // disable receive
#define F2_DIAG_LOOP_EN      0x00000040 // enable tx-rx loopback
#define F2_DIAG_CORR_FCS     0x00000080 // corrupt FCS
#define F2_DIAG_CHAN_INFO    0x00000100 // dump channel info
#define F2_DIAG_EN_SCRAMSD   0x00000200 // enable fixed scrambler seed
#define F2_DIAG_SCRAM_SEED_M 0x0001FC00 // Mask for fixed scrambler seed
#define F2_DIAG_SCRAM_SEED_S 10         // Shift for fixed scrambler seed
#define F2_DIAG_FRAME_NV0    0x00020000 // accept frames of non-zero protocol version
#define F2_DIAG_OBS_PT_SEL_M 0x000C0000 // Mask for observation point select
#define F2_DIAG_OBS_PT_SEL_S 18         // Shift for observation point select

#define F2_TSF_L32          0x804c  // MAC local clock lower 32 bits
#define F2_TSF_U32          0x8050  // MAC local clock upper 32 bits

#define F2_DEF_ANT			0x8058 //default antenna register
 
#define F2_LAST_TSTP        0x8080  // MAC Time stamp of the last beacon received
#define F2_NAV              0x8084  // MAC current NAV value
#define F2_RTS_OK           0x8088  // MAC RTS exchange success counter
#define F2_RTS_FAIL         0x808c  // MAC RTS exchange failure counter
#define F2_ACK_FAIL         0x8090  // MAC ACK failure counter
#define F2_FCS_FAIL         0x8094  // FCS check failure counter
#define F2_BEACON_CNT       0x8098  // Valid beacon counter


//
// Key table is 128 entries of 8 double-words each
//
#ifndef SWIG // SWIG cannot parse structures
#define D2_KEY_TABLE		0x8800
#define D2_KEY_NUM_ENTRIES	128
typedef struct D2KeyTableEntry
{
	A_UINT32	KeyVal0;
	A_UINT32	KeyVal1;
	A_UINT32	KeyVal2;
	A_UINT32	KeyVal3;
	A_UINT32	KeyVal4;
	A_UINT32	KeyType;
	A_UINT32	MacAddrLo;
	A_UINT32	MacAddrHi;
} D2_KEY_TABLE_ENTRY;

#define D2_KEY_TYPE_M			0x00000007
#define D2_KEY_TYPE_WEP_40		0
#define D2_KEY_TYPE_WEP_104		1
#define D2_KEY_TYPE_WEP_128		3
#define D2_KEY_TYPE_WEP2		4	
#define D2_KEY_TYPE_AES			5
#define D2_KEY_TYPE_LAST_TX_ANT 0x00000008	//last tx antenna

#ifdef ARCH_BIG_ENDIAN
typedef struct 
{
	A_UINT32	Reserved4:16,
				KeyValid:1,
				MacAddrHi:15;
} MAC_ADDR_HI_KEY_VALID;
#else
typedef struct 
{
	A_UINT32	MacAddrHi:15,
				KeyValid:1,
				Reserved4:16;
} MAC_ADDR_HI_KEY_VALID;
#endif /* ARCH_BIG_ENDIAN */
#endif // #ifndef SWIG

// PHY registers
#define PHY_BASE            0x9800  // PHY registers base address

#define PHY_FRAME_CONTROL   0x9804  // PHY frame control register (this is really called turbo now
#define PHY_FC_TURBO_MODE    0x00000001 // Set turbo mode bits
#define PHY_FC_TURBO_SHORT   0x00000002 // Set short symbols to turbo mode setting

#define PHY_FRAME_CONTROL1   0x9944  // rest of old PHY frame control register
#define PHY_FC_TIMING_ERR    0x01000000 // Detect PHY timing error
#define PHY_FC_PARITY_ERR    0x02000000 // Detect PHY signal parity error
#define PHY_FC_ILLRATE_ERR   0x04000000 // Detect PHY illegal rate error
#define PHY_FC_ILLLEN_ERR    0x08000000 // Detect PHY illegal length error
#define PHY_FC_SERVICE_ERR   0x20000000 // Detect PHY non-zero service bytes error
#define PHY_FC_TX_UNDER_ERR  0x40000000 // Detect PHY transmit underrun error

#define PHY_CHIP_ID         0x9818  // PHY chip revision ID

#define PHY_ACTIVE          0x981C  // PHY activation register
#define PHY_ACTIVE_EN        0x00000001 // Activate PHY chips
#define PHY_ACTIVE_DIS       0x00000000 // Deactivate PHY chips

#define PHY_AGC_CONTROL     0x9860  // PHY chip calibration and noise floor setting
#define PHY_AGC_CONTROL_CAL  0x00000001 // Perform PHY chip internal calibration
#define PHY_AGC_CONTROL_NF   0x00000002 // Perform PHY chip noise-floor calculation

#define PHY_RX_DELAY		0x9914	// PHY analog_power_on_time, in 100ns increments
#define PHY_RX_DELAY_M		0x00003FFF // Mask for delay from active assertion (wake up)
									   // to enable_receiver

#define PHY_TIMING_CTRL4	0x9920	// PHY 
#define PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M		0x0000001F // Mask for kcos_theta-1 for q correction
#define PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_M		0x000007E0 // Mask for sin_theta for i correction
#define PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S		5		   // Shift for sin_theta for i correction
#define PHY_TIMING_CTRL4_IQCORR_ENABLE			0x00000800 // enable IQ correction 
#define PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_M	0x0000F000 // Mask for max number of samples (logarithmic)
#define PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S	12		   // Shift for max number of samples 
#define PHY_TIMING_CTRL4_DO_IQCAL				0x00010000 // perform IQ calibration  

#define PHY_IQCAL_RES_PWR_MEAS_I	0x9c10	//PHY IQ calibration results - power measurement for I  
#define PHY_IQCAL_RES_PWR_MEAS_Q	0x9c14	//PHY IQ calibration results - power measurement for Q  
#define PHY_IQCAL_RES_IQ_CORR_MEAS	0x9c18	//PHY IQ calibration results - IQ correlation measurement

// Device ID defines for AR5211 devices
#define DEV_AR5211_PCI      0x0111
#define DEV_AR5211_PC       0x0011
#define DEV_AR5211_AP       0x0211
#define DEV_LEGACY          0x1107

#endif