📄 ar5211reg.h
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#define F2_D3_RETRY_LIMIT 0x108c // MAC Retry limits
#define F2_D4_RETRY_LIMIT 0x1090 // MAC Retry limits
#define F2_D5_RETRY_LIMIT 0x1094 // MAC Retry limits
#define F2_D6_RETRY_LIMIT 0x1098 // MAC Retry limits
#define F2_D7_RETRY_LIMIT 0x109c // MAC Retry limits
#define F2_D8_RETRY_LIMIT 0x10a0 // MAC Retry limits
#define F2_D9_RETRY_LIMIT 0x10a4 // MAC Retry limits
#define F2_D10_RETRY_LIMIT 0x10a8 // MAC Retry limits
#define F2_D_RETRY_LIMIT_FR_SH_M 0x0000000F // Mask for frame short retry limit
#define F2_D_RETRY_LIMIT_FR_LG_M 0x000000F0 // Mask for frame long retry limit
#define F2_D_RETRY_LIMIT_STA_SH_M 0x00003F00 // Mask for station short retry limit
#define F2_D_RETRY_LIMIT_STA_LG_M 0x000FC000 // Mask for station short retry limit
#define F2_D_RETRY_LIMIT_RESV0 0xFFF00000 // Reserved
#define F2_D0_CHNTIME 0x10c0 // MAC ChannelTime settings
#define F2_D1_CHNTIME 0x10c4 // MAC ChannelTime settings
#define F2_D2_CHNTIME 0x10c8 // MAC ChannelTime settings
#define F2_D3_CHNTIME 0x10cc // MAC ChannelTime settings
#define F2_D4_CHNTIME 0x10d0 // MAC ChannelTime settings
#define F2_D5_CHNTIME 0x10d4 // MAC ChannelTime settings
#define F2_D6_CHNTIME 0x10d8 // MAC ChannelTime settings
#define F2_D7_CHNTIME 0x10dc // MAC ChannelTime settings
#define F2_D8_CHNTIME 0x10e0 // MAC ChannelTime settings
#define F2_D9_CHNTIME 0x10e4 // MAC ChannelTime settings
#define F2_D10_CHNTIME 0x10e8 // MAC ChannelTime settings
#define F2_D_CHNTIME_DUR_M 0x000FFFFF // Mask for ChannelTime duration (us)
#define F2_D_CHNTIME_EN 0x00100000 // ChannelTime enable
#define F2_D_CHNTIME_RESV0 0xFFE00000 // Reserved
#define F2_D0_MISC 0x1100 // MAC Miscellaneous DCU-specific settings
#define F2_D1_MISC 0x1104 // MAC Miscellaneous DCU-specific settings
#define F2_D2_MISC 0x1108 // MAC Miscellaneous DCU-specific settings
#define F2_D3_MISC 0x110c // MAC Miscellaneous DCU-specific settings
#define F2_D4_MISC 0x1110 // MAC Miscellaneous DCU-specific settings
#define F2_D5_MISC 0x1114 // MAC Miscellaneous DCU-specific settings
#define F2_D6_MISC 0x1118 // MAC Miscellaneous DCU-specific settings
#define F2_D7_MISC 0x111c // MAC Miscellaneous DCU-specific settings
#define F2_D8_MISC 0x1120 // MAC Miscellaneous DCU-specific settings
#define F2_D9_MISC 0x1124 // MAC Miscellaneous DCU-specific settings
#define F2_D10_MISC 0x1128 // MAC Miscellaneous DCU-specific settings
#define F2_D_MISC_BKOFF_THRESH_M 0x000007FF // Mask for Backoff threshold setting
#define F2_D_MISC_HCF_POLL_EN 0x00000800 // HFC poll enable
#define F2_D_MISC_BKOFF_PERSISTENCE 0x00001000 // Backoff persistence factor setting
#define F2_D_MISC_FR_PREFETCH_EN 0x00002000 // Frame prefetch enable
#define F2_D_MISC_VIR_COL_HANDLING_M 0x0000C000 // Mask for Virtual collision handling policy
#define F2_D_MISC_VIR_COL_HANDLING_NORMAL 0 // Normal
#define F2_D_MISC_VIR_COL_HANDLING_MODIFIED 1 // Modified
#define F2_D_MISC_VIR_COL_HANDLING_IGNORE 2 // Ignore
#define F2_D_MISC_BEACON_USE 0x00010000 // Beacon use indication
#define F2_D_MISC_ARB_LOCKOUT_CNTRL_M 0x00060000 // Mask for DCU arbiter lockout control
#define F2_D_MISC_ARB_LOCKOUT_CNTRL_S 17 // Shift for DCU arbiter lockout control
#define F2_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 // No lockout
#define F2_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 // Intra-frame
#define F2_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 // Global
#define F2_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 // DCU arbiter lockout ignore control
#define F2_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 // Sequence number increment disable
#define F2_D_MISC_POST_FR_BKOFF_DIS 0x00200000 // Post-frame backoff disable
#define F2_D_MISC_VIRT_COLL_POLICY 0x00400000 // Virtual coll. handling policy
#define F2_D_MISC_BLOWN_IFS_POLICY 0x00800000 // Blown IFS handling policy
#define F2_D_MISC_SEQ_NUM_CONTROL 0x01000000 // Sequence Number local or global
#define F2_D_MISC_RESV0 0xFE000000 // Reserved
#define F2_D0_SEQNUM 0x1140 // MAC Frame sequence number control/status
#define F2_D1_SEQNUM 0x1144 // MAC Frame sequence number control/status
#define F2_D2_SEQNUM 0x1148 // MAC Frame sequence number control/status
#define F2_D3_SEQNUM 0x114c // MAC Frame sequence number control/status
#define F2_D4_SEQNUM 0x1150 // MAC Frame sequence number control/status
#define F2_D5_SEQNUM 0x1154 // MAC Frame sequence number control/status
#define F2_D6_SEQNUM 0x1158 // MAC Frame sequence number control/status
#define F2_D7_SEQNUM 0x115c // MAC Frame sequence number control/status
#define F2_D8_SEQNUM 0x1160 // MAC Frame sequence number control/status
#define F2_D9_SEQNUM 0x1164 // MAC Frame sequence number control/status
#define F2_D10_SEQNUM 0x1168 // MAC Frame sequence number control/status
#define F2_D_SEQNUM_M 0x00000FFF // Mask for value of sequence number
#define F2_D_SEQNUM_RESV0 0xFFFFF000 // Reserved
#define F2_D_GBL_IFS_SIFS 0x1030 // MAC DCU-global IFS settings: SIFS duration
#define F2_D_GBL_IFS_SIFS_M 0x0000FFFF // Mask for SIFS duration (core clocks)
#define F2_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF // Reserved
#define F2_D_GBL_IFS_SLOT 0x1070 // MAC DCU-global IFS settings: slot duration
#define F2_D_GBL_IFS_SLOT_M 0x0000FFFF // Mask for Slot duration (core clocks)
#define F2_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 // Reserved
#define F2_D_GBL_IFS_EIFS 0x10b0 // MAC DCU-global IFS settings: EIFS duration
#define F2_D_GBL_IFS_EIFS_M 0x0000FFFF // Mask for Slot duration (core clocks)
#define F2_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 // Reserved
#define F2_D_GBL_IFS_MISC 0x10f0 // MAC DCU-global IFS settings: Miscellaneous
#define F2_D_GBL_IFS_MISC_LFSR_SLICE_SEL_M 0x00000007 // Mask forLFSR slice select
#define F2_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 // Turbo mode indication
#define F2_D_GBL_IFS_MISC_SIFS_DURATION_USEC_M 0x000003F0 // Mask for SIFS duration (us)
#define F2_D_GBL_IFS_MISC_USEC_DURATION_M 0x000FFC00 // Mask for microsecond duration
#define F2_D_GBL_IFS_MISC_DCU_ARBITER_DLY_M 0x00300000 // Mask for DCU arbiter delay
#define F2_D_GBL_IFS_MISC_RESV0 0xFFC00000 // Reserved
#define F2_D_FPCTL 0x1230 //Frame prefetch
#define F2_D_TXBLK_BASE 0x00001038
#define CALC_MMR(dcu, idx) ( (4 * dcu) + \
(idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
#define TXBLK_FROM_MMR(mmr) (F2_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3))
#define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx)))
#define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f))
// DMA & PCI Registers in PCI space (usable during sleep)
#define F2_RC 0x4000 // Warm reset control register
#define F2_RC_MAC 0x00000001 // MAC reset
#define F2_RC_BB 0x00000002 // Baseband reset
#define F2_RC_RESV0 0x00000004 // Reserved
#define F2_RC_RESV1 0x00000008 // Reserved
#define F2_RC_PCI 0x00000010 // PCI-core reset
#define F2_SCR 0x4004 // Sleep control register
#define F2_SCR_SLDUR_MASK 0x0000ffff // sleep duration mask, units of 128us
#define F2_SCR_SLE_MASK 0x00030000 // sleep enable mask
#define F2_SCR_SLE_FWAKE 0x00000000 // force wake
#define F2_SCR_SLE_FSLEEP 0x00010000 // force sleep
#define F2_SCR_SLE_NORMAL 0x00020000 // sleep logic normal operation
#define F2_SCR_SLE_UNITS 0x00000008 // SCR units/TU
#define F2_INTPEND 0x4008 // Interrupt Pending register
#define F2_INTPEND_TRUE 0x00000001 // interrupt pending
#define F2_SFR 0x400C // Sleep force register
#define F2_SFR_SLEEP 0x00000001 // force sleep
#define F2_SFR_WAKE 0x00000002 // force wake
#define F2_PCICFG 0x4010 // PCI configuration register
#define F2_PCICFG_SLEEP_CLK_SEL 0x00000002 // select between 40MHz normal or 32KHz sleep clock
#define F2_PCICFG_CLKRUNEN 0x00000004 // enable PCI CLKRUN function
#define F2_PCICFG_EEPROM_SIZE_M 0x00000018 // Mask for EEPROM size
#define F2_PCICFG_EEPROM_SIZE_4K 0 // EEPROM size 4 Kbit
#define F2_PCICFG_EEPROM_SIZE_8K 1 // EEPROM size 4 Kbit
#define F2_PCICFG_EEPROM_SIZE_16K 2 // EEPROM size 4 Kbit
#define F2_PCICFG_EEPROM_SIZE_FAILED 3 // Failure
#define F2_PCICFG_ASSOC_STATUS_M 0x00000060 // Mask for Association Status
#define F2_PCICFG_ASSOC_STATUS_NONE 0
#define F2_PCICFG_ASSOC_STATUS_PENDING 1
#define F2_PCICFG_ASSOC_STATUS_ASSOCIATED 2
#define F2_PCICFG_PCI_BUS_SEL_M 0x00000380 // Mask for PCI observation bus mux select
#define F2_PCICFG_DIS_CBE_FIX 0x00000400 // Disable fix for bad PCI CBE# generation
#define F2_PCICFG_SL_INTEN 0x00000800 // enable interrupt line assertion when asleep
#define F2_PCICFG_RESV0 0x00001000 // Reserved
#define F2_PCICFG_SL_INPEN 0x00002000 // Force asleep when an interrupt is pending
#define F2_PCICFG_RESV1 0x0000C000 // Reserved
#define F2_PCICFG_SPWR_DN 0x00010000 // mask for sleep/awake indication
#define F2_PCICFG_LED_MODE_M 0x000E0000 // Mask for LED mode select
#define F2_PCICFG_LED_BLINK_THRESHOLD_M 0x00700000 // Mask for LED blink threshold select
#define F2_PCICFG_LED_SLOW_BLINK_MODE 0x00800000 // LED slowest blink rate mode
#define F2_PCICFG_SLEEP_CLK_RATE_INDICATION 0x03000000 // LED slowest blink rate mode
#define F2_PCICFG_RESV2 0xFF000000 // Reserved
#define F2_NUM_GPIO 6 // Six numbered 0 to 5.
#define F2_GPIOCR 0x4014 // GPIO control register
#define F2_GPIOCR_CR_SHIFT 2 // Each CR is 2 bits
#define F2_GPIOCR_0_CR_N 0x00000000 // Input only mode for GPIODO[0]
#define F2_GPIOCR_0_CR_0 0x00000001 // Output only if GPIODO[0] = 0
#define F2_GPIOCR_0_CR_1 0x00000002 // Output only if GPIODO[0] = 1
#define F2_GPIOCR_0_CR_A 0x00000003 // Always output
#define F2_GPIOCR_1_CR_N 0x00000000 // Input only mode for GPIODO[1]
#define F2_GPIOCR_1_CR_0 0x00000004 // Output only if GPIODO[1] = 0
#define F2_GPIOCR_1_CR_1 0x00000008 // Output only if GPIODO[1] = 1
#define F2_GPIOCR_1_CR_A 0x0000000C // Always output
#define F2_GPIOCR_2_CR_N 0x00000000 // Input only mode for GPIODO[2]
#define F2_GPIOCR_2_CR_0 0x00000010 // Output only if GPIODO[2] = 0
#define F2_GPIOCR_2_CR_1 0x00000020 // Output only if GPIODO[2] = 1
#define F2_GPIOCR_2_CR_A 0x00000030 // Always output
#define F2_GPIOCR_3_CR_N 0x00000000 // Input only mode for GPIODO[3]
#define F2_GPIOCR_3_CR_0 0x00000040 // Output only if GPIODO[3] = 0
#define F2_GPIOCR_3_CR_1 0x00000080 // Output only if GPIODO[3] = 1
#define F2_GPIOCR_3_CR_A 0x000000C0 // Always output
#define F2_GPIOCR_4_CR_N 0x00000000 // Input only mode for GPIODO[4]
#define F2_GPIOCR_4_CR_0 0x00000100 // Output only if GPIODO[4] = 0
#define F2_GPIOCR_4_CR_1 0x00000200 // Output only if GPIODO[4] = 1
#define F2_GPIOCR_4_CR_A 0x00000300 // Always output
#define F2_GPIOCR_5_CR_N 0x00000000 // Input only mode for GPIODO[5]
#define F2_GPIOCR_5_CR_0 0x00000400 // Output only if GPIODO[5] = 0
#define F2_GPIOCR_5_CR_1 0x00000800 // Output only if GPIODO[5] = 1
#define F2_GPIOCR_5_CR_A 0x00000C00 // Always output
#define F2_GPIOCR_INT_SEL0 0x00000000 // Select Interrupt Pin GPIO_0
#define F2_GPIOCR_INT_SEL1 0x00001000 // Select Interrupt Pin GPIO_1
#define F2_GPIOCR_INT_SEL2 0x00002000 // Select Interrupt Pin GPIO_2
#define F2_GPIOCR_INT_SEL3 0x00003000 // Select Interrupt Pin GPIO_3
#define F2_GPIOCR_INT_SEL4 0x00004000 // Select Interrupt Pin GPIO_4
#define F2_GPIOCR_INT_SEL5 0x00005000 // Select Interrupt Pin GPIO_5
#define F2_GPIOCR_INT_EN 0x00008000 // Enable GPIO Interrupt
#define F2_GPIOCR_INT_SELL 0x00000000 // Generate Interrupt if selected pin is low
#define F2_GPIOCR_INT_SELH 0x00010000 // Generate Interrupt if selected pin is high
#define F2_GPIODO 0x4018 // GPIO data output access register
#define F2_GPIODI 0x401C // GPIO data input access register
#define F2_GPIOD_MASK 0x0000002F // Mask for reading or writing GPIO data regs
#define F2_SREV 0x4020 // Silicon Revision register
#define F2_SREV_ID_M 0x000000FF // Mask to read SREV info
#define F2_SREV_REVISION_M 0x0000000F // Mask for Chip revision level
#define F2_SREV_FPGA 1
#define F2_SREV_D2PLUS 2
#define F2_SREV_D2PLUS_MS 3 // metal spin
#define F2_SREV_CRETE 4
#define F2_SREV_CRETE_MS 5 // FCS metal spin
#define F2_SREV_CRETE_MS23 7 // 2.3 metal spin (6 skipped)
#define F2_SREV_CRETE_23 8 // 2.3 full tape out
#define F2_SREV_VERSION_M 0x000000F0 // Mask for Chip version indication
#define F2_SREV_VERSION_CRETE 0
#define F2_SREV_VERSION_MAUI_1 1
#define F2_SREV_VERSION_MAUI_2 2
// EEPROM Registers in the MAC
#define F2_EEPROM_ADDR 0x6000 // EEPROM address register (10 bit)
#define F2_EEPROM_DATA 0x6004 // EEPROM data register (16 bit)
#define F2_EEPROM_CMD 0x6008 // EEPROM command register
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