📄 ar5211reg.h
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#define F2_IMR_S4 0x00b4 // MAC Secondary interrupt mask register 4
#define F2_IMR_S4_QCU_QTRIG_M 0x0000FFFF // Mask for QTRIG (QCU 0-15)
#define F2_IMR_S4_RESV0 0xFFFF0000 // Reserved
// Interrupt status registers (read-and-clear access, secondary shadow copies)
#define F2_ISR_RAC 0x00c0 // MAC Primary interrupt status register,
// read-and-clear access
#define F2_ISR_S0_S 0x00c4 // MAC Secondary interrupt status register 0,
// shadow copy
#define F2_ISR_S1_S 0x00c8 // MAC Secondary interrupt status register 1,
// shadow copy
#define F2_ISR_S2_S 0x00cc // MAC Secondary interrupt status register 2,
// shadow copy
#define F2_ISR_S3_S 0x00d0 // MAC Secondary interrupt status register 3,
// shadow copy
#define F2_ISR_S4_S 0x00d4 // MAC Secondary interrupt status register 4,
// shadow copy
// QCU registers
#define F2_NUM_QCU 16 // 0-15
#define F2_QCU_0 0x0001
#define F2_QCU_1 0x0002
#define F2_QCU_2 0x0004
#define F2_QCU_3 0x0008
#define F2_QCU_4 0x0010
#define F2_QCU_5 0x0020
#define F2_QCU_6 0x0040
#define F2_QCU_7 0x0080
#define F2_QCU_8 0x0100
#define F2_QCU_9 0x0200
#define F2_QCU_10 0x0400
#define F2_QCU_11 0x0800
#define F2_QCU_12 0x1000
#define F2_QCU_13 0x2000
#define F2_QCU_14 0x4000
#define F2_QCU_15 0x8000
#define F2_Q0_TXDP 0x0800 // MAC Transmit Queue descriptor pointer
#define F2_Q1_TXDP 0x0804 // MAC Transmit Queue descriptor pointer
#define F2_Q2_TXDP 0x0808 // MAC Transmit Queue descriptor pointer
#define F2_Q3_TXDP 0x080c // MAC Transmit Queue descriptor pointer
#define F2_Q4_TXDP 0x0810 // MAC Transmit Queue descriptor pointer
#define F2_Q5_TXDP 0x0814 // MAC Transmit Queue descriptor pointer
#define F2_Q6_TXDP 0x0818 // MAC Transmit Queue descriptor pointer
#define F2_Q7_TXDP 0x081c // MAC Transmit Queue descriptor pointer
#define F2_Q8_TXDP 0x0820 // MAC Transmit Queue descriptor pointer
#define F2_Q9_TXDP 0x0824 // MAC Transmit Queue descriptor pointer
#define F2_Q10_TXDP 0x0828 // MAC Transmit Queue descriptor pointer
#define F2_Q11_TXDP 0x082c // MAC Transmit Queue descriptor pointer
#define F2_Q12_TXDP 0x0830 // MAC Transmit Queue descriptor pointer
#define F2_Q13_TXDP 0x0834 // MAC Transmit Queue descriptor pointer
#define F2_Q14_TXDP 0x0838 // MAC Transmit Queue descriptor pointer
#define F2_Q15_TXDP 0x083c // MAC Transmit Queue descriptor pointer
#define F2_Q_TXE 0x0840 // MAC Transmit Queue enable
#define F2_Q_TXE_M 0x0000FFFF // Mask for TXE (QCU 0-15)
#define F2_Q_TXD 0x0880 // MAC Transmit Queue disable
#define F2_Q_TXD_M 0x0000FFFF // Mask for TXD (QCU 0-15)
#define F2_Q0_CBRCFG 0x08c0 // MAC CBR configuration
#define F2_Q1_CBRCFG 0x08c4 // MAC CBR configuration
#define F2_Q2_CBRCFG 0x08c8 // MAC CBR configuration
#define F2_Q3_CBRCFG 0x08cc // MAC CBR configuration
#define F2_Q4_CBRCFG 0x08d0 // MAC CBR configuration
#define F2_Q5_CBRCFG 0x08d4 // MAC CBR configuration
#define F2_Q6_CBRCFG 0x08d8 // MAC CBR configuration
#define F2_Q7_CBRCFG 0x08dc // MAC CBR configuration
#define F2_Q8_CBRCFG 0x08e0 // MAC CBR configuration
#define F2_Q9_CBRCFG 0x08e4 // MAC CBR configuration
#define F2_Q10_CBRCFG 0x08e8 // MAC CBR configuration
#define F2_Q11_CBRCFG 0x08ec // MAC CBR configuration
#define F2_Q12_CBRCFG 0x08f0 // MAC CBR configuration
#define F2_Q13_CBRCFG 0x08f4 // MAC CBR configuration
#define F2_Q14_CBRCFG 0x08f8 // MAC CBR configuration
#define F2_Q15_CBRCFG 0x08fc // MAC CBR configuration
#define F2_Q_CBRCFG_CBR_INTERVAL_M 0x00FFFFFF // Mask for CBR interval (us)
#define F2_Q_CBRCFG_CBR_OVF_THRESH_M 0xFF000000 // Mask for CBR overflow threshold
#define F2_Q0_RDYTIMECFG 0x0900 // MAC ReadyTime configuration
#define F2_Q1_RDYTIMECFG 0x0904 // MAC ReadyTime configuration
#define F2_Q2_RDYTIMECFG 0x0908 // MAC ReadyTime configuration
#define F2_Q3_RDYTIMECFG 0x090c // MAC ReadyTime configuration
#define F2_Q4_RDYTIMECFG 0x0910 // MAC ReadyTime configuration
#define F2_Q5_RDYTIMECFG 0x0914 // MAC ReadyTime configuration
#define F2_Q6_RDYTIMECFG 0x0918 // MAC ReadyTime configuration
#define F2_Q7_RDYTIMECFG 0x091c // MAC ReadyTime configuration
#define F2_Q8_RDYTIMECFG 0x0920 // MAC ReadyTime configuration
#define F2_Q9_RDYTIMECFG 0x0924 // MAC ReadyTime configuration
#define F2_Q10_RDYTIMECFG 0x0928 // MAC ReadyTime configuration
#define F2_Q11_RDYTIMECFG 0x092c // MAC ReadyTime configuration
#define F2_Q12_RDYTIMECFG 0x0930 // MAC ReadyTime configuration
#define F2_Q13_RDYTIMECFG 0x0934 // MAC ReadyTime configuration
#define F2_Q14_RDYTIMECFG 0x0938 // MAC ReadyTime configuration
#define F2_Q15_RDYTIMECFG 0x093c // MAC ReadyTime configuration
#define F2_Q_RDYTIMECFG_DURATION_M 0x00FFFFFF // Mask for CBR interval (us)
#define F2_Q_RDYTIMECFG_EN 0x01000000 // ReadyTime enable
#define F2_Q_RDYTIMECFG_RESV0 0xFE000000 // Reserved
#define F2_Q_ONESHOTARM_SC 0x0940 // MAC OneShotArm set control
#define F2_Q_ONESHOTARM_SC_M 0x0000FFFF // Mask for F2_Q_ONESHOTARM_SC (QCU 0-15)
#define F2_Q_ONESHOTARM_SC_RESV0 0xFFFF0000 // Reserved
#define F2_Q_ONESHOTARM_CC 0x0980 // MAC OneShotArm clear control
#define F2_Q_ONESHOTARM_CC_M 0x0000FFFF // Mask for F2_Q_ONESHOTARM_CC (QCU 0-15)
#define F2_Q_ONESHOTARM_CC_RESV0 0xFFFF0000 // Reserved
#define F2_Q0_MISC 0x09c0 // MAC Miscellaneous QCU settings
#define F2_Q1_MISC 0x09c4 // MAC Miscellaneous QCU settings
#define F2_Q2_MISC 0x09c8 // MAC Miscellaneous QCU settings
#define F2_Q3_MISC 0x09cc // MAC Miscellaneous QCU settings
#define F2_Q4_MISC 0x09d0 // MAC Miscellaneous QCU settings
#define F2_Q5_MISC 0x09d4 // MAC Miscellaneous QCU settings
#define F2_Q6_MISC 0x09d8 // MAC Miscellaneous QCU settings
#define F2_Q7_MISC 0x09dc // MAC Miscellaneous QCU settings
#define F2_Q8_MISC 0x09e0 // MAC Miscellaneous QCU settings
#define F2_Q9_MISC 0x09e4 // MAC Miscellaneous QCU settings
#define F2_Q10_MISC 0x09e8 // MAC Miscellaneous QCU settings
#define F2_Q11_MISC 0x09ec // MAC Miscellaneous QCU settings
#define F2_Q12_MISC 0x09f0 // MAC Miscellaneous QCU settings
#define F2_Q13_MISC 0x09f4 // MAC Miscellaneous QCU settings
#define F2_Q14_MISC 0x09f8 // MAC Miscellaneous QCU settings
#define F2_Q15_MISC 0x09fc // MAC Miscellaneous QCU settings
#define F2_Q_MISC_FSP_M 0x0000000F // Mask for Frame Scheduling Policy
#define F2_Q_MISC_FSP_ASAP 0 // ASAP
#define F2_Q_MISC_FSP_CBR 1 // CBR
#define F2_Q_MISC_FSP_DBA_GATED 2 // DMA Beacon Alert gated
#define F2_Q_MISC_FSP_TIM_GATED 3 // TIM gated
#define F2_Q_MISC_FSP_BEACON_SENT_GATED 4 // Beacon-sent-gated
#define F2_Q_MISC_ONE_SHOT_EN 0x00000010 // OneShot enable
#define F2_Q_MISC_CBR_INCR_DIS1 0x00000020 // Disable CBR expired counter incr (empty q)
#define F2_Q_MISC_CBR_INCR_DIS0 0x00000040 // Disable CBR expired counter incr (empty beacon q)
#define F2_Q_MISC_BEACON_USE 0x00000080 // Beacon use indication
#define F2_Q_MISC_CBR_EXP_CNTR_LIMIT 0x00000100 // CBR expired counter limit enable
#define F2_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 // Enable TXE cleared on ReadyTime expired or VEOL
#define F2_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 // Reset CBR expired counter
#define F2_Q_MISC_RESV0 0xFFFFF000 // Reserved
#define F2_Q0_STS 0x0a00 // MAC Miscellaneous QCU status
#define F2_Q1_STS 0x0a04 // MAC Miscellaneous QCU status
#define F2_Q2_STS 0x0a08 // MAC Miscellaneous QCU status
#define F2_Q3_STS 0x0a0c // MAC Miscellaneous QCU status
#define F2_Q4_STS 0x0a10 // MAC Miscellaneous QCU status
#define F2_Q5_STS 0x0a14 // MAC Miscellaneous QCU status
#define F2_Q6_STS 0x0a18 // MAC Miscellaneous QCU status
#define F2_Q7_STS 0x0a1c // MAC Miscellaneous QCU status
#define F2_Q8_STS 0x0a20 // MAC Miscellaneous QCU status
#define F2_Q9_STS 0x0a24 // MAC Miscellaneous QCU status
#define F2_Q10_STS 0x0a28 // MAC Miscellaneous QCU status
#define F2_Q11_STS 0x0a2c // MAC Miscellaneous QCU status
#define F2_Q12_STS 0x0a30 // MAC Miscellaneous QCU status
#define F2_Q13_STS 0x0a34 // MAC Miscellaneous QCU status
#define F2_Q14_STS 0x0a38 // MAC Miscellaneous QCU status
#define F2_Q15_STS 0x0a3c // MAC Miscellaneous QCU status
#define F2_Q_STS_PEND_FR_CNT_M 0x00000003 // Mask for Pending Frame Count
#define F2_Q_STS_RESV0 0x000000FC // Reserved
#define F2_Q_STS_CBR_EXP_CNT_M 0x0000FF00 // Mask for CBR expired counter
#define F2_Q_STS_RESV1 0xFFFF0000 // Reserved
#define F2_Q_RDYTIMESHDN 0x0a40 // MAC ReadyTimeShutdown status
#define F2_Q_RDYTIMESHDN_M 0x0000FFFF // Mask for ReadyTimeShutdown status (QCU 0-15)
// DCU registers
#define F2_NUM_DCU 11 // 0-10
#define F2_DCU_0 0x0001
#define F2_DCU_1 0x0002
#define F2_DCU_2 0x0004
#define F2_DCU_3 0x0008
#define F2_DCU_4 0x0010
#define F2_DCU_5 0x0020
#define F2_DCU_6 0x0040
#define F2_DCU_7 0x0080
#define F2_DCU_8 0x0100
#define F2_DCU_9 0x0200
#define F2_DCU_10 0x0400
#define F2_DCU_11 0x0800
#define F2_D0_QCUMASK 0x1000 // MAC QCU Mask
#define F2_D1_QCUMASK 0x1004 // MAC QCU Mask
#define F2_D2_QCUMASK 0x1008 // MAC QCU Mask
#define F2_D3_QCUMASK 0x100c // MAC QCU Mask
#define F2_D4_QCUMASK 0x1010 // MAC QCU Mask
#define F2_D5_QCUMASK 0x1014 // MAC QCU Mask
#define F2_D6_QCUMASK 0x1018 // MAC QCU Mask
#define F2_D7_QCUMASK 0x101c // MAC QCU Mask
#define F2_D8_QCUMASK 0x1020 // MAC QCU Mask
#define F2_D9_QCUMASK 0x1024 // MAC QCU Mask
#define F2_D10_QCUMASK 0x1028 // MAC QCU Mask
#define F2_D_QCUMASK_M 0x0000FFFF // Mask for QCU Mask (QCU 0-15)
#define F2_D_QCUMASK_RESV0 0xFFFF0000 // Reserved
#define F2_D0_LCL_IFS 0x1040 // MAC DCU-specific IFS settings
#define F2_D1_LCL_IFS 0x1044 // MAC DCU-specific IFS settings
#define F2_D2_LCL_IFS 0x1048 // MAC DCU-specific IFS settings
#define F2_D3_LCL_IFS 0x104c // MAC DCU-specific IFS settings
#define F2_D4_LCL_IFS 0x1050 // MAC DCU-specific IFS settings
#define F2_D5_LCL_IFS 0x1054 // MAC DCU-specific IFS settings
#define F2_D6_LCL_IFS 0x1058 // MAC DCU-specific IFS settings
#define F2_D7_LCL_IFS 0x105c // MAC DCU-specific IFS settings
#define F2_D8_LCL_IFS 0x1060 // MAC DCU-specific IFS settings
#define F2_D9_LCL_IFS 0x1064 // MAC DCU-specific IFS settings
#define F2_D10_LCL_IFS 0x1068 // MAC DCU-specific IFS settings
#define F2_D_LCL_IFS_CWMIN_M 0x000003FF // Mask for CW_MIN
#define F2_D_LCL_IFS_CWMAX_M 0x000FFC00 // Mask for CW_MAX
#define F2_D_LCL_IFS_CWMAX_S 10 // Shift for CW_MAX
#define F2_D_LCL_IFS_AIFS_M 0x0FF00000 // Mask for AIFS
#define F2_D_LCL_IFS_AIFS_S 20 // Shift for AIFS
#define F2_D_LCL_IFS_RESV0 0xF0000000 // Reserved
#define F2_D0_RETRY_LIMIT 0x1080 // MAC Retry limits
#define F2_D1_RETRY_LIMIT 0x1084 // MAC Retry limits
#define F2_D2_RETRY_LIMIT 0x1088 // MAC Retry limits
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