ar5211reg.h

Atheros AP Test with Agilent N4010A source code

#ifndef __ARREGH__
#define __ARREGH__


/*
 *  Copyright (c) 2001 Atheros Communications, Inc., All Rights Reserved
 */

/* ar5211reg.h Register definitions for Atheros AR5211 chipset */

#ident  "ACI $Header: //depot/sw/branches/ART_V53_dragon/sw/src/dk/mdk/devlib/ar5211/ar5211reg.h#1 $"

// DMA Control and Interrupt Registers
#define F2_CR               0x0008  // MAC Control Register - only write values of 1 have effect
#define F2_CR_RXE            0x00000004 // Receive enable
#define F2_CR_RXD            0x00000020 // Receive disable
#define F2_CR_SWI            0x00000040 // One-shot software interrupt

#define F2_RXDP             0x000C  // MAC receive queue descriptor pointer

#define F2_CFG              0x0014  // MAC configuration and status register
#define F2_CFG_SWTD          0x00000001 // byteswap tx descriptor words
#define F2_CFG_SWTB          0x00000002 // byteswap tx data buffer words
#define F2_CFG_SWRD          0x00000004 // byteswap rx descriptor words
#define F2_CFG_SWRB          0x00000008 // byteswap rx data buffer words
#define F2_CFG_SWRG          0x00000010 // byteswap register access data words
#define F2_CFG_AP_ADHOC_INDICATION				0x00000020 // AP/adhoc indication (0-AP, 1-Adhoc)
#define F2_CFG_PHOK          0x00000100 // PHY OK status
#define F2_CFG_EEBS          0x00000200 // EEPROM busy
#define F2_CFG_PCI_MASTER_REQ_Q_THRESH_M       0x00060000 // Mask of PCI core master request queue full threshold
#define F2_CFG_PCI_MASTER_REQ_Q_THRESH_S       17         // Shift for PCI core master request queue full threshold


#define F2_IER              0x0024  // MAC Interrupt enable register
#define F2_IER_ENABLE        0x00000001 // Global interrupt enable
#define F2_IER_DISABLE       0x00000000 // Global interrupt disable


#define F2_RTSD0            0x0028  // MAC RTS Duration Parameters 0
#define F2_RTSD0_RTS_DURATION_6_M	0x000000FF	
#define F2_RTSD0_RTS_DURATION_6_S	0
#define F2_RTSD0_RTS_DURATION_9_M	0x0000FF00	
#define F2_RTSD0_RTS_DURATION_9_S	8
#define F2_RTSD0_RTS_DURATION_12_M	0x00FF0000	
#define F2_RTSD0_RTS_DURATION_12_S	16	
#define F2_RTSD0_RTS_DURATION_18_M	0xFF000000
#define F2_RTSD0_RTS_DURATION_18_S	24

#define F2_RTSD1            0x002c  // MAC RTS Duration Parameters 1
#define F2_RTSD0_RTS_DURATION_24_M	0x000000FF	
#define F2_RTSD0_RTS_DURATION_24_S	0
#define F2_RTSD0_RTS_DURATION_36_M	0x0000FF00	
#define F2_RTSD0_RTS_DURATION_36_S	8
#define F2_RTSD0_RTS_DURATION_48_M	0x00FF0000
#define F2_RTSD0_RTS_DURATION_48_S	16
#define F2_RTSD0_RTS_DURATION_54_M	0xFF000000
#define F2_RTSD0_RTS_DURATION_54_S	24


#define F2_TXCFG            0x0030  // MAC tx DMA size config register
#define F2_TXCFG_CONT_EN     0x00000008 // Enable continuous transmit mode

#define F2_RXCFG            0x0034  // MAC rx DMA size config register

#define F2_RXCFG_DEF_RX_ANTENNA		0x00000008 // Default Receive Antenna
#define F2_RXCFG_ZLFDMA      0x00000010 // Enable DMA of zero-length frame
#define F2_DMASIZE_4B        0x00000000 // DMA size 4 bytes 
#define F2_DMASIZE_8B        0x00000001 // DMA size 8 bytes 
#define F2_DMASIZE_16B       0x00000002 // DMA size 16 bytes 
#define F2_DMASIZE_32B       0x00000003 // DMA size 32 bytes 
#define F2_DMASIZE_64B       0x00000004 // DMA size 64 bytes 
#define F2_DMASIZE_128B      0x00000005 // DMA size 128 bytes 
#define F2_DMASIZE_256B      0x00000006 // DMA size 256 bytes 
#define F2_DMASIZE_512B      0x00000007 // DMA size 512 bytes 

#define F2_MIBC             0x0040  // MAC MIB control register
#define F2_MIBC_COW          0x00000001 // counter overflow warning
#define F2_MIBC_FMC          0x00000002 // freeze MIB counters
#define F2_MIBC_CMC          0x00000004 // clear MIB counters
#define F2_MIBC_MCS          0x00000008 // MIB counter strobe, increment all

#define F2_TOPS             0x0044  // MAC timeout prescale count
#define F2_TOPS_MASK         0x0000FFFF // Mask for timeout prescale

#define F2_RXNPTO           0x0048  // MAC no frame received timeout
#define F2_RXNPTO_MASK       0x000003FF // Mask for no frame received timeout

#define F2_TXNPTO           0x004C  // MAC no frame trasmitted timeout
#define F2_TXNPTO_MASK       0x000003FF // Mask for no frame transmitted timeout
#define F2_TXNPTO_QCU_MASK   0x03FFFC00 // Mask indicating the set of QCUs
									// for which frame completions will cause
									// a reset of the no frame transmitted timeout 

#define F2_RPGTO            0x0050  // MAC receive frame gap timeout
#define F2_RPGTO_MASK        0x000003FF // Mask for receive frame gap timeout

#define F2_RPCNT            0x0054 // MAC receive frame count limit
#define F2_RPCNT_MASK        0x0000001F // Mask for receive frame count limit
  
#define F2_MACMISC           0x0058 // MAC miscellaneous control/status register
#define F2_MACMISC_DMA_OBS_M    0x000001E0 // Mask for DMA observation bus mux select
#define F2_MACMISC_DMA_OBS_S    5          // Shift for DMA observation bus mux select
#define F2_MACMISC_MISC_OBS_M   0x00000E00 // Mask for MISC observation bus mux select
#define F2_MACMISC_MISC_OBS_S   9          // Shift for MISC observation bus mux select
#define F2_MACMISC_MAC_OBS_BUS_LSB_M   0x00007000 // Mask for MAC observation bus mux select (lsb)
#define F2_MACMISC_MAC_OBS_BUS_LSB_S   12         // Shift for MAC observation bus mux select (lsb)
#define F2_MACMISC_MAC_OBS_BUS_MSB_M   0x00038000 // Mask for MAC observation bus mux select (msb)
#define F2_MACMISC_MAC_OBS_BUS_MSB_S   15         // Shift for MAC observation bus mux select (msb)

#define F2_QDCKLGATE         0x005c // MAC QCU/DCU clock gating control register
#define F2_QDCKLGATE_QCU_M    0x0000FFFF // Mask for QCU clock disable 
#define F2_QDCKLGATE_DCU_M    0x07FF0000 // Mask for DCU clock disable 

// Interrupt Status Registers

#define F2_ISR             0x0080 // MAC Primary interrupt status register
#define F2_ISR_RXOK          0x00000001 // At least one frame received sans errors
#define F2_ISR_RXDESC        0x00000002 // Receive interrupt request
#define F2_ISR_RXERR         0x00000004 // Receive error interrupt
#define F2_ISR_RXNOPKT       0x00000008 // No frame received within timeout clock
#define F2_ISR_RXEOL         0x00000010 // Received descriptor empty interrupt
#define F2_ISR_RXORN         0x00000020 // Receive FIFO overrun interrupt
#define F2_ISR_TXOK          0x00000040 // Transmit okay interrupt
#define F2_ISR_TXDESC        0x00000080 // Transmit interrupt request
#define F2_ISR_TXERR         0x00000100 // Transmit error interrupt
#define F2_ISR_TXNOPKT       0x00000200 // No frame transmitted interrupt
#define F2_ISR_TXEOL         0x00000400 // Transmit descriptor empty interrupt
#define F2_ISR_TXURN         0x00000800 // Transmit FIFO underrun interrupt
#define F2_ISR_MIB           0x00001000 // MIB interrupt - see MIBC
#define F2_ISR_SWI           0x00002000 // Software interrupt
#define F2_ISR_RXPHY         0x00004000 // PHY receive error interrupt
#define F2_ISR_RXKCM         0x00008000 // Key-cache miss interrupt
#define F2_ISR_SWBA          0x00010000 // Software beacon alert interrupt
#define F2_ISR_BRSSI         0x00020000 // Beacon threshold interrupt
#define F2_ISR_BMISS         0x00040000 // Beacon missed interrupt
#define F2_ISR_HIUERR        0x00080000 // An unexpected bus error has occurred
#define F2_ISR_BNR		   0x00100000 // Beacon not ready interrupt
#define F2_ISR_TIM		   0x00800000 // TIM interrupt
#define F2_ISR_GPIO          0x01000000 // GPIO Interrupt
#define F2_ISR_QCBROVF       0x02000000 // QCU CBR overflow interrupt
#define F2_ISR_QCBRURN       0x04000000 // QCU CBR underrun interrupt
#define F2_ISR_QTRIG         0x08000000 // QCU scheduling trigger interrupt
#define F2_ISR_RESV0         0xF0000000 // Reserved

#define F2_ISR_S0             0x0084 // MAC Secondary interrupt status register 0
#define F2_ISR_S0_QCU_TXOK_M    0x0000FFFF // Mask for TXOK (QCU 0-15)
#define F2_ISR_S0_QCU_TXDESC_M  0xFFFF0000 // Mask for TXDESC (QCU 0-15)

#define F2_ISR_S1             0x0088 // MAC Secondary interrupt status register 1
#define F2_ISR_S1_QCU_TXERR_M  0x0000FFFF // Mask for TXERR (QCU 0-15)
#define F2_ISR_S1_QCU_TXEOL_M  0xFFFF0000 // Mask for TXEOL (QCU 0-15)
 
#define F2_ISR_S2             0x008c // MAC Secondary interrupt status register 2
#define F2_ISR_S2_QCU_TXURN_M  0x0000FFFF // Mask for TXURN (QCU 0-15)
#define F2_ISR_S2_MCABT        0x00010000 // Master cycle abort interrupt
#define F2_ISR_S2_SSERR        0x00020000 // SERR interrupt
#define F2_ISR_S2_DPERR        0x00040000 // PCI bus parity error
#define F2_ISR_S2_RESV0        0xFFF80000 // Reserved

#define F2_ISR_S3             0x0090 // MAC Secondary interrupt status register 3
#define F2_ISR_S3_QCU_QCBROVF_M  0x0000FFFF // Mask for QCBROVF (QCU 0-15)
#define F2_ISR_S3_QCU_QCBRURN_M  0xFFFF0000 // Mask for QCBRURN (QCU 0-15)

#define F2_ISR_S4             0x0094 // MAC Secondary interrupt status register 4
#define F2_ISR_S4_QCU_QTRIG_M  0x0000FFFF // Mask for QTRIG (QCU 0-15)
#define F2_ISR_S4_RESV0        0xFFFF0000 // Reserved

// Interrupt Mask Registers

#define F2_IMR             0x00a0  // MAC Primary interrupt mask register
#define F2_IMR_RXOK          0x00000001 // At least one frame received sans errors
#define F2_IMR_RXDESC        0x00000002 // Receive interrupt request
#define F2_IMR_RXERR         0x00000004 // Receive error interrupt
#define F2_IMR_RXNOPKT       0x00000008 // No frame received within timeout clock
#define F2_IMR_RXEOL         0x00000010 // Received descriptor empty interrupt
#define F2_IMR_RXORN         0x00000020 // Receive FIFO overrun interrupt
#define F2_IMR_TXOK          0x00000040 // Transmit okay interrupt
#define F2_IMR_TXDESC        0x00000080 // Transmit interrupt request
#define F2_IMR_TXERR         0x00000100 // Transmit error interrupt
#define F2_IMR_TXNOPKT       0x00000200 // No frame transmitted interrupt
#define F2_IMR_TXEOL         0x00000400 // Transmit descriptor empty interrupt
#define F2_IMR_TXURN         0x00000800 // Transmit FIFO underrun interrupt
#define F2_IMR_MIB           0x00001000 // MIB interrupt - see MIBC
#define F2_IMR_SWI           0x00002000 // Software interrupt
#define F2_IMR_RXPHY         0x00004000 // PHY receive error interrupt
#define F2_IMR_RXKCM         0x00008000 // Key-cache miss interrupt
#define F2_IMR_SWBA          0x00010000 // Software beacon alert interrupt
#define F2_IMR_BRSSI         0x00020000 // Beacon threshold interrupt
#define F2_IMR_BMISS         0x00040000 // Beacon missed interrupt
#define F2_IMR_HIUERR        0x00080000 // An unexpected bus error has occurred
#define F2_IMR_BNR           0x00100000 // BNR interrupt
#define F2_IMR_TIM		   0x00800000 // TIM interrupt
#define F2_IMR_GPIO          0x01000000 // GPIO Interrupt
#define F2_IMR_QCBROVF       0x02000000 // QCU CBR overflow interrupt
#define F2_IMR_QCBRURN       0x04000000 // QCU CBR underrun interrupt
#define F2_IMR_QTRIG         0x08000000 // QCU scheduling trigger interrupt
#define F2_IMR_RESV0         0xF0000000 // Reserved


#define F2_IMR_S0             0x00a4 // MAC Secondary interrupt mask register 0
#define F2_IMR_S0_QCU_TXOK_M    0x0000FFFF // Mask for TXOK (QCU 0-15)
#define F2_IMR_S0_QCU_TXDESC_M  0xFFFF0000 // Mask for TXDESC (QCU 0-15)
#define F2_IMR_S0_QCU_TXDESC_S  16		   // Shift for TXDESC (QCU 0-15)

#define F2_IMR_S1             0x00a8 // MAC Secondary interrupt mask register 1
#define F2_IMR_S1_QCU_TXERR_M  0x0000FFFF // Mask for TXERR (QCU 0-15)
#define F2_IMR_S1_QCU_TXEOL_M  0xFFFF0000 // Mask for TXEOL (QCU 0-15)
#define F2_IMR_S1_QCU_TXEOL_S  16		  // Shift for TXEOL (QCU 0-15)
 
#define F2_IMR_S2             0x00ac // MAC Secondary interrupt mask register 2
#define F2_IMR_S2_QCU_TXURN_M  0x0000FFFF // Mask for TXURN (QCU 0-15)
#define F2_IMR_S2_MCABT        0x00010000 // Master cycle abort interrupt
#define F2_IMR_S2_SSERR        0x00020000 // SERR interrupt
#define F2_IMR_S2_DPERR        0x00040000 // PCI bus parity error
#define F2_IMR_S2_RESV0        0xFFF80000 // Reserved

#define F2_IMR_S3             0x00b0 // MAC Secondary interrupt mask register 3
#define F2_IMR_S3_QCU_QCBROVF_M  0x0000FFFF // Mask for QCBROVF (QCU 0-15)
#define F2_IMR_S3_QCU_QCBRURN_M  0xFFFF0000 // Mask for QCBRURN (QCU 0-15)
#define F2_IMR_S3_QCU_QCBRURN_S  16		    // Shift for QCBRURN (QCU 0-15)