liangzhu.tan.qmsg

FPGA音乐试验

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "sys_clk 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"sys_clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "sp~reg0 sp~reg0 sys_clk 982 ps " "Info: Found hold time violation between source  pin or register \"sp~reg0\" and destination pin or register \"sp~reg0\" for clock \"sys_clk\" (Hold time is 982 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.205 ns + Largest " "Info: + Largest clock skew is 2.205 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk destination 12.952 ns + Longest register " "Info: + Longest clock path from clock \"sys_clk\" to destination register is 12.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_153 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[2\] 2 REG LC_X8_Y12_N5 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y12_N5; Fanout = 17; REG Node = 'clk_cnt\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[2] } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.265 ns) + CELL(0.935 ns) 8.349 ns divider\[2\] 3 REG LC_X15_Y12_N5 4 " "Info: 3: + IC(4.265 ns) + CELL(0.935 ns) = 8.349 ns; Loc. = LC_X15_Y12_N5; Fanout = 4; REG Node = 'divider\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.200 ns" { clk_cnt[2] divider[2] } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.590 ns) 9.702 ns Equal0~162 4 COMB LC_X15_Y12_N0 1 " "Info: 4: + IC(0.763 ns) + CELL(0.590 ns) = 9.702 ns; Loc. = LC_X15_Y12_N0; Fanout = 1; COMB Node = 'Equal0~162'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.353 ns" { divider[2] Equal0~162 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.214 ns) + CELL(0.590 ns) 11.506 ns Equal0~166 5 COMB LC_X15_Y11_N8 15 " "Info: 5: + IC(1.214 ns) + CELL(0.590 ns) = 11.506 ns; Loc. = LC_X15_Y11_N8; Fanout = 15; COMB Node = 'Equal0~166'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.804 ns" { Equal0~162 Equal0~166 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.735 ns) + CELL(0.711 ns) 12.952 ns sp~reg0 6 REG LC_X14_Y11_N2 2 " "Info: 6: + IC(0.735 ns) + CELL(0.711 ns) = 12.952 ns; Loc. = LC_X14_Y11_N2; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.446 ns" { Equal0~166 sp~reg0 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.230 ns ( 40.38 % ) " "Info: Total cell delay = 5.230 ns ( 40.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.722 ns ( 59.62 % ) " "Info: Total interconnect delay = 7.722 ns ( 59.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.952 ns" { sys_clk clk_cnt[2] divider[2] Equal0~162 Equal0~166 sp~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.952 ns" { sys_clk sys_clk~out0 clk_cnt[2] divider[2] Equal0~162 Equal0~166 sp~reg0 } { 0.000ns 0.000ns 0.745ns 4.265ns 0.763ns 1.214ns 0.735ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk source 10.747 ns - Shortest register " "Info: - Shortest clock path from clock \"sys_clk\" to source register is 10.747 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_153 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[2\] 2 REG LC_X8_Y12_N5 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y12_N5; Fanout = 17; REG Node = 'clk_cnt\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[2] } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.265 ns) + CELL(0.935 ns) 8.349 ns divider\[13\] 3 REG LC_X15_Y11_N6 2 " "Info: 3: + IC(4.265 ns) + CELL(0.935 ns) = 8.349 ns; Loc. = LC_X15_Y11_N6; Fanout = 2; REG Node = 'divider\[13\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.200 ns" { clk_cnt[2] divider[13] } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.114 ns) 9.005 ns Equal0~165 4 COMB LC_X15_Y11_N7 1 " "Info: 4: + IC(0.542 ns) + CELL(0.114 ns) = 9.005 ns; Loc. = LC_X15_Y11_N7; Fanout = 1; COMB Node = 'Equal0~165'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.656 ns" { divider[13] Equal0~165 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 9.301 ns Equal0~166 5 COMB LC_X15_Y11_N8 15 " "Info: 5: + IC(0.182 ns) + CELL(0.114 ns) = 9.301 ns; Loc. = LC_X15_Y11_N8; Fanout = 15; COMB Node = 'Equal0~166'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { Equal0~165 Equal0~166 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.735 ns) + CELL(0.711 ns) 10.747 ns sp~reg0 6 REG LC_X14_Y11_N2 2 " "Info: 6: + IC(0.735 ns) + CELL(0.711 ns) = 10.747 ns; Loc. = LC_X14_Y11_N2; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.446 ns" { Equal0~166 sp~reg0 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.278 ns ( 39.81 % ) " "Info: Total cell delay = 4.278 ns ( 39.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.469 ns ( 60.19 % ) " "Info: Total interconnect delay = 6.469 ns ( 60.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.747 ns" { sys_clk clk_cnt[2] divider[13] Equal0~165 Equal0~166 sp~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.747 ns" { sys_clk sys_clk~out0 clk_cnt[2] divider[13] Equal0~165 Equal0~166 sp~reg0 } { 0.000ns 0.000ns 0.745ns 4.265ns 0.542ns 0.182ns 0.735ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.114ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.952 ns" { sys_clk clk_cnt[2] divider[2] Equal0~162 Equal0~166 sp~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.952 ns" { sys_clk sys_clk~out0 clk_cnt[2] divider[2] Equal0~162 Equal0~166 sp~reg0 } { 0.000ns 0.000ns 0.745ns 4.265ns 0.763ns 1.214ns 0.735ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.747 ns" { sys_clk clk_cnt[2] divider[13] Equal0~165 Equal0~166 sp~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.747 ns" { sys_clk sys_clk~out0 clk_cnt[2] divider[13] Equal0~165 Equal0~166 sp~reg0 } { 0.000ns 0.000ns 0.745ns 4.265ns 0.542ns 0.182ns 0.735ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.114ns 0.114ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 32 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.014 ns - Shortest register register " "Info: - Shortest register to register delay is 1.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sp~reg0 1 REG LC_X14_Y11_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y11_N2; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sp~reg0 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.536 ns) + CELL(0.478 ns) 1.014 ns sp~reg0 2 REG LC_X14_Y11_N2 2 " "Info: 2: + IC(0.536 ns) + CELL(0.478 ns) = 1.014 ns; Loc. = LC_X14_Y11_N2; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.014 ns" { sp~reg0 sp~reg0 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns ( 47.14 % ) " "Info: Total cell delay = 0.478 ns ( 47.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.536 ns ( 52.86 % ) " "Info: Total interconnect delay = 0.536 ns ( 52.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.014 ns" { sp~reg0 sp~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.014 ns" { sp~reg0 sp~reg0 } { 0.000ns 0.536ns } { 0.000ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 32 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.952 ns" { sys_clk clk_cnt[2] divider[2] Equal0~162 Equal0~166 sp~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.952 ns" { sys_clk sys_clk~out0 clk_cnt[2] divider[2] Equal0~162 Equal0~166 sp~reg0 } { 0.000ns 0.000ns 0.745ns 4.265ns 0.763ns 1.214ns 0.735ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.747 ns" { sys_clk clk_cnt[2] divider[13] Equal0~165 Equal0~166 sp~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.747 ns" { sys_clk sys_clk~out0 clk_cnt[2] divider[13] Equal0~165 Equal0~166 sp~reg0 } { 0.000ns 0.000ns 0.745ns 4.265ns 0.542ns 0.182ns 0.735ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.114ns 0.114ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.014 ns" { sp~reg0 sp~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.014 ns" { sp~reg0 sp~reg0 } { 0.000ns 0.536ns } { 0.000ns 0.478ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sys_clk sp sp~reg0 18.578 ns register " "Info: tco from clock \"sys_clk\" to destination pin \"sp\" through register \"sp~reg0\" is 18.578 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk source 12.952 ns + Longest register " "Info: + Longest clock path from clock \"sys_clk\" to source register is 12.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_153 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[2\] 2 REG LC_X8_Y12_N5 17 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y12_N5; Fanout = 17; REG Node = 'clk_cnt\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[2] } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.265 ns) + CELL(0.935 ns) 8.349 ns divider\[2\] 3 REG LC_X15_Y12_N5 4 " "Info: 3: + IC(4.265 ns) + CELL(0.935 ns) = 8.349 ns; Loc. = LC_X15_Y12_N5; Fanout = 4; REG Node = 'divider\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.200 ns" { clk_cnt[2] divider[2] } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.590 ns) 9.702 ns Equal0~162 4 COMB LC_X15_Y12_N0 1 " "Info: 4: + IC(0.763 ns) + CELL(0.590 ns) = 9.702 ns; Loc. = LC_X15_Y12_N0; Fanout = 1; COMB Node = 'Equal0~162'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.353 ns" { divider[2] Equal0~162 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.214 ns) + CELL(0.590 ns) 11.506 ns Equal0~166 5 COMB LC_X15_Y11_N8 15 " "Info: 5: + IC(1.214 ns) + CELL(0.590 ns) = 11.506 ns; Loc. = LC_X15_Y11_N8; Fanout = 15; COMB Node = 'Equal0~166'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.804 ns" { Equal0~162 Equal0~166 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.735 ns) + CELL(0.711 ns) 12.952 ns sp~reg0 6 REG LC_X14_Y11_N2 2 " "Info: 6: + IC(0.735 ns) + CELL(0.711 ns) = 12.952 ns; Loc. = LC_X14_Y11_N2; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.446 ns" { Equal0~166 sp~reg0 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.230 ns ( 40.38 % ) " "Info: Total cell delay = 5.230 ns ( 40.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.722 ns ( 59.62 % ) " "Info: Total interconnect delay = 7.722 ns ( 59.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.952 ns" { sys_clk clk_cnt[2] divider[2] Equal0~162 Equal0~166 sp~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.952 ns" { sys_clk sys_clk~out0 clk_cnt[2] divider[2] Equal0~162 Equal0~166 sp~reg0 } { 0.000ns 0.000ns 0.745ns 4.265ns 0.763ns 1.214ns 0.735ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 32 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.402 ns + Longest register pin " "Info: + Longest register to pin delay is 5.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sp~reg0 1 REG LC_X14_Y11_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y11_N2; Fanout = 2; REG Node = 'sp~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sp~reg0 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.294 ns) + CELL(2.108 ns) 5.402 ns sp 2 PIN PIN_62 0 " "Info: 2: + IC(3.294 ns) + CELL(2.108 ns) = 5.402 ns; Loc. = PIN_62; Fanout = 0; PIN Node = 'sp'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.402 ns" { sp~reg0 sp } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 39.02 % ) " "Info: Total cell delay = 2.108 ns ( 39.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.294 ns ( 60.98 % ) " "Info: Total interconnect delay = 3.294 ns ( 60.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.402 ns" { sp~reg0 sp } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.402 ns" { sp~reg0 sp } { 0.000ns 3.294ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.952 ns" { sys_clk clk_cnt[2] divider[2] Equal0~162 Equal0~166 sp~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.952 ns" { sys_clk sys_clk~out0 clk_cnt[2] divider[2] Equal0~162 Equal0~166 sp~reg0 } { 0.000ns 0.000ns 0.745ns 4.265ns 0.763ns 1.214ns 0.735ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.590ns 0.590ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.402 ns" { sp~reg0 sp } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.402 ns" { sp~reg0 sp } { 0.000ns 3.294ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}