liangzhu.tan.qmsg

FPGA音乐试验

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sys_clk " "Info: Assuming node \"sys_clk\" is an undefined clock" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 2 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sys_clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "20 " "Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_cnt\[23\] " "Info: Detected ripple clock \"clk_cnt\[23\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 9 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_cnt\[23\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[13\] " "Info: Detected ripple clock \"divider\[13\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[12\] " "Info: Detected ripple clock \"divider\[12\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[11\] " "Info: Detected ripple clock \"divider\[11\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[10\] " "Info: Detected ripple clock \"divider\[10\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[9\] " "Info: Detected ripple clock \"divider\[9\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[8\] " "Info: Detected ripple clock \"divider\[8\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[7\] " "Info: Detected ripple clock \"divider\[7\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[6\] " "Info: Detected ripple clock \"divider\[6\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[5\] " "Info: Detected ripple clock \"divider\[5\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[4\] " "Info: Detected ripple clock \"divider\[4\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[3\] " "Info: Detected ripple clock \"divider\[3\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[2\] " "Info: Detected ripple clock \"divider\[2\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[1\] " "Info: Detected ripple clock \"divider\[1\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_cnt\[2\] " "Info: Detected ripple clock \"clk_cnt\[2\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 9 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk_cnt\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~165 " "Info: Detected gated clock \"Equal0~165\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 19 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~165" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~164 " "Info: Detected gated clock \"Equal0~164\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 19 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~164" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~163 " "Info: Detected gated clock \"Equal0~163\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 19 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~163" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Equal0~162 " "Info: Detected gated clock \"Equal0~162\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 19 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Equal0~162" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "divider\[0\] " "Info: Detected ripple clock \"divider\[0\]\" as buffer" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "divider\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sys_clk memory altsyncram:WideOr13_rtl_0\|altsyncram_3iu:auto_generated\|ram_block1a3~porta_address_reg0 register origin\[4\] 93.71 MHz 10.671 ns Internal " "Info: Clock \"sys_clk\" has Internal fmax of 93.71 MHz between source memory \"altsyncram:WideOr13_rtl_0\|altsyncram_3iu:auto_generated\|ram_block1a3~porta_address_reg0\" and destination register \"origin\[4\]\" (period= 10.671 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.955 ns + Longest memory register " "Info: + Longest memory to register delay is 9.955 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:WideOr13_rtl_0\|altsyncram_3iu:auto_generated\|ram_block1a3~porta_address_reg0 1 MEM M4K_X17_Y12 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y12; Fanout = 4; MEM Node = 'altsyncram:WideOr13_rtl_0\|altsyncram_3iu:auto_generated\|ram_block1a3~porta_address_reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_3iu.tdf" "" { Text "E:/AJian/FPGA/LiangZhu/db/altsyncram_3iu.tdf" 97 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns altsyncram:WideOr13_rtl_0\|altsyncram_3iu:auto_generated\|q_a\[2\] 2 MEM M4K_X17_Y12 9 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X17_Y12; Fanout = 9; MEM Node = 'altsyncram:WideOr13_rtl_0\|altsyncram_3iu:auto_generated\|q_a\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.308 ns" { altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|q_a[2] } "NODE_NAME" } } { "db/altsyncram_3iu.tdf" "" { Text "E:/AJian/FPGA/LiangZhu/db/altsyncram_3iu.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.158 ns) + CELL(0.442 ns) 5.908 ns Equal1~141 3 COMB LC_X22_Y12_N7 3 " "Info: 3: + IC(1.158 ns) + CELL(0.442 ns) = 5.908 ns; Loc. = LC_X22_Y12_N7; Fanout = 3; COMB Node = 'Equal1~141'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|q_a[2] Equal1~141 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.292 ns) 6.636 ns Equal1~143 4 COMB LC_X22_Y12_N5 3 " "Info: 4: + IC(0.436 ns) + CELL(0.292 ns) = 6.636 ns; Loc. = LC_X22_Y12_N5; Fanout = 3; COMB Node = 'Equal1~143'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.728 ns" { Equal1~141 Equal1~143 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.442 ns) 7.808 ns WideNor0~102 5 COMB LC_X21_Y12_N3 5 " "Info: 5: + IC(0.730 ns) + CELL(0.442 ns) = 7.808 ns; Loc. = LC_X21_Y12_N3; Fanout = 5; COMB Node = 'WideNor0~102'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.172 ns" { Equal1~143 WideNor0~102 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 8.104 ns WideNor0~106 6 COMB LC_X21_Y12_N4 3 " "Info: 6: + IC(0.182 ns) + CELL(0.114 ns) = 8.104 ns; Loc. = LC_X21_Y12_N4; Fanout = 3; COMB Node = 'WideNor0~106'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { WideNor0~102 WideNor0~106 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.542 ns) + CELL(0.309 ns) 9.955 ns origin\[4\] 7 REG LC_X15_Y12_N2 1 " "Info: 7: + IC(1.542 ns) + CELL(0.309 ns) = 9.955 ns; Loc. = LC_X15_Y12_N2; Fanout = 1; REG Node = 'origin\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.851 ns" { WideNor0~106 origin[4] } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.907 ns ( 59.34 % ) " "Info: Total cell delay = 5.907 ns ( 59.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.048 ns ( 40.66 % ) " "Info: Total interconnect delay = 4.048 ns ( 40.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.955 ns" { altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|q_a[2] Equal1~141 Equal1~143 WideNor0~102 WideNor0~106 origin[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.955 ns" { altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|q_a[2] Equal1~141 Equal1~143 WideNor0~102 WideNor0~106 origin[4] } { 0.000ns 0.000ns 1.158ns 0.436ns 0.730ns 0.182ns 1.542ns } { 0.000ns 4.308ns 0.442ns 0.292ns 0.442ns 0.114ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.029 ns - Smallest " "Info: - Smallest clock skew is -0.029 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk destination 7.369 ns + Shortest register " "Info: + Shortest clock path from clock \"sys_clk\" to destination register is 7.369 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_153 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[23\] 2 REG LC_X8_Y10_N6 34 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 34; REG Node = 'clk_cnt\[23\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[23] } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.711 ns) 7.369 ns origin\[4\] 3 REG LC_X15_Y12_N2 1 " "Info: 3: + IC(3.509 ns) + CELL(0.711 ns) = 7.369 ns; Loc. = LC_X15_Y12_N2; Fanout = 1; REG Node = 'origin\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.220 ns" { clk_cnt[23] origin[4] } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.27 % ) " "Info: Total cell delay = 3.115 ns ( 42.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.254 ns ( 57.73 % ) " "Info: Total interconnect delay = 4.254 ns ( 57.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.369 ns" { sys_clk clk_cnt[23] origin[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.369 ns" { sys_clk sys_clk~out0 clk_cnt[23] origin[4] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clk source 7.398 ns - Longest memory " "Info: - Longest clock path from clock \"sys_clk\" to source memory is 7.398 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sys_clk 1 CLK PIN_153 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 24; CLK Node = 'sys_clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sys_clk } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clk_cnt\[23\] 2 REG LC_X8_Y10_N6 34 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 34; REG Node = 'clk_cnt\[23\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { sys_clk clk_cnt[23] } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.527 ns) + CELL(0.722 ns) 7.398 ns altsyncram:WideOr13_rtl_0\|altsyncram_3iu:auto_generated\|ram_block1a3~porta_address_reg0 3 MEM M4K_X17_Y12 4 " "Info: 3: + IC(3.527 ns) + CELL(0.722 ns) = 7.398 ns; Loc. = M4K_X17_Y12; Fanout = 4; MEM Node = 'altsyncram:WideOr13_rtl_0\|altsyncram_3iu:auto_generated\|ram_block1a3~porta_address_reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.249 ns" { clk_cnt[23] altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_3iu.tdf" "" { Text "E:/AJian/FPGA/LiangZhu/db/altsyncram_3iu.tdf" 97 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.126 ns ( 42.25 % ) " "Info: Total cell delay = 3.126 ns ( 42.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.272 ns ( 57.75 % ) " "Info: Total interconnect delay = 4.272 ns ( 57.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.398 ns" { sys_clk clk_cnt[23] altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.398 ns" { sys_clk sys_clk~out0 clk_cnt[23] altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 } { 0.000ns 0.000ns 0.745ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.369 ns" { sys_clk clk_cnt[23] origin[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.369 ns" { sys_clk sys_clk~out0 clk_cnt[23] origin[4] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.398 ns" { sys_clk clk_cnt[23] altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.398 ns" { sys_clk sys_clk~out0 clk_cnt[23] altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 } { 0.000ns 0.000ns 0.745ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_3iu.tdf" "" { Text "E:/AJian/FPGA/LiangZhu/db/altsyncram_3iu.tdf" 97 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "liangzhu.v" "" { Text "E:/AJian/FPGA/LiangZhu/liangzhu.v" 51 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.955 ns" { altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|q_a[2] Equal1~141 Equal1~143 WideNor0~102 WideNor0~106 origin[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.955 ns" { altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|q_a[2] Equal1~141 Equal1~143 WideNor0~102 WideNor0~106 origin[4] } { 0.000ns 0.000ns 1.158ns 0.436ns 0.730ns 0.182ns 1.542ns } { 0.000ns 4.308ns 0.442ns 0.292ns 0.442ns 0.114ns 0.309ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.369 ns" { sys_clk clk_cnt[23] origin[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.369 ns" { sys_clk sys_clk~out0 clk_cnt[23] origin[4] } { 0.000ns 0.000ns 0.745ns 3.509ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.398 ns" { sys_clk clk_cnt[23] altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.398 ns" { sys_clk sys_clk~out0 clk_cnt[23] altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 } { 0.000ns 0.000ns 0.745ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.722ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}