initialization.c

blackfin开发板 BF533-UART开发代码 开发环境为visul dsp 3.5

#include "system.h"
#include "ccblkfn.h"
#include "sysreg.h"

#include <sys\exception.h>
#include <cdefBF533.h>



void Init_PLL(void)
{
    int iIMASK_Value;
	sysreg_write(reg_SYSCFG, 0x32);		//Initialize System Configuration Register

	// set VCO/CCLK = 1, and VCO/SCLK = 5 (take effect immediately)
	*pPLL_DIV = 0x0005;

	// prepare PLL changes (set CLKIN/VCO = 22; takes effect after PLL programming sequence)
	*pPLL_LOCKCNT	= 0x0200;					// time for PLL to stabilize
	*pPLL_CTL		= 0x2c00;					// set VCO/CLKIN = 24

	// execute PLL programming sequence
	*pSIC_IWR		= 0x00000001;				// enable only PLL wakeup interrupt
	iIMASK_Value	= cli();					// disable interrupts
	idle();										// wait for PLL wakeup interrupt
	sti(iIMASK_Value);	
}//end Init_PLL 

void Init_UART(void)
{
	*pUART_GCTL = 0x0001;	//UART Global Control Register
							//UCEN=1(Enable UART Clocks)
							//	1:Enable UART clocks
							//	0:Disable UART clocks
							//IREN=0(Enable IrDA Mode)
							//	1:Enable IrDA
							//	0:Disable IrDA
							//TPOLC=0(IrDA TX Polarity Change)
							//	1:Serial line idles high
							//	0:Serial line idles low
							//RPOLC=0(IrDA RX Polarity Change)
							//	1:Serial line idles high
							//	0:Serial line idles low
							//FPE=0(Force Parity Error on Transmit)
							//	1:Force error
							//	0:Normal operation
							//FFE=0(Force Framing Error on Transmit)
							//	1:Force error
							//	0:Normal operaion
	*pUART_LCR = 0x0083;		//UART Line Control Register, prepare for DLL and DLH setting
	asm("ssync;");
	*pUART_DLL = 0x002B;		//43
	*pUART_DLH = 0x0000;		//UART Divisor Latch Registers
							
	asm("ssync;");
	*pUART_LCR = 0x0003;		//UART Line Control Register
							//WLS[1:0]=11(Word Length Select)
							//	00:5-bit word
							//	01:6-bit word
							//	10:7-bit word
							//	11:8-bit word
							//STB=0(Stop Bits)
							//	1:2 stop bits for non-5-bit word length or 1/2 stop bits for 5-bit word length
							//	0:1 stop bit
							//PEN=0(Parity Enable)
							// 	1:Transmit and check parity
							//	0:Parity not transmitted or checked
							//EPS=0(Even Parity Select)
							//	1:Even parity
							//	0:Odd parity when PEN=1 and STP=0
							//STP=0(Stick Parity)
							//	1:Force parity to defined value if set and PEN=1
							//		EPS=1,parity transmitted and checked as 0
							//		EPS=0,parity transmitted and checked as 1
							//	0:Normal ???
							//SB=0(Set Break)
							//	0:Not force
							//	1:Force TX pin to 0
							//DLAB=0(Divisor Latch Access)
							//	1:Enable access to UART_DLL and UART_DLH
							//	0:Enable access to UART_THR,UART_RBR and UART_IER
	asm("ssync;");
	*pUART_MCR = 0x0000;	//Modem Control Register
							//Loop=0(Loopback mode enable)
							//Forces TX to high and disconnects RX from RSR
	*pUART_IER = 0x0001;		//UART Interrupt Enable Register
							//ERBFI=1(Enable Receive Buffer Full Interrupt)
							//	0:No interrupt
							//	1:Generate RX interrupt if DR bit in UART_LSR is set
							//ETBEI=0(Enable Transmit Buffer Empty Interrupt)
							//	0:No interrrupt
							//	1:Generate TX interrupt if THRE bit in UART_LSR is set
							//ELSI=0(Enable RX Status Interrupt)
							//	0:No interrupt
							//	1:Generate line status interrupt if any of UART_LSR[4:1] is set
	asm("ssync;");
}

void Init_SDRAM(void)
{

	*pEBIU_SDRRC =  0x00000817;	//SDRAM Refresh Rate Control Register
	*pEBIU_SDBCTL = 0x00000001;	//SDRAM Memory Bank Control Register
	*pEBIU_SDGCTL = 0x0091998d;	//SDRAM Memory Global Control Register

	asm("ssync;");
}

void Init_EBIU(void)
{
	*pEBIU_AMBCTL0	= 0x7bb07bb0;
	*pEBIU_AMBCTL1	= 0x7bb07bb0;
	*pEBIU_AMGCTL	= 0x000f;

	*pLight = 0xFF; // All lights off
	*pLed = 0xFF;
}

void Init_Interrupts(void)
{
	// assign core IDs to interrupts
	*pSIC_IAR0 = 0xffffffff;
	*pSIC_IAR1 = 0xf4ffffff;					// UART -> ID4
	*pSIC_IAR2 = 0xffffffff;

	// assign ISRs to interrupt vectors
	register_handler(ik_ivg11, UART_ISR);		// UART ISR -> IVG 11

	// enable Timer0 and FlagA interrupt
	*pSIC_IMASK = 0x00004000;
}