📄 vga4.rpt
字号:
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 1 8 8 0 0 8 8 8 8 8 73/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 7 0 8 1 8 0 0 0 8 0 0 0 0 8 8 8 1 8 8 8 8 3 7 5 3 107/0
Total: 7 0 8 1 8 0 0 0 8 0 0 0 0 16 16 9 9 16 8 8 16 11 15 13 11 180/0
Device-Specific Information: d:\max2workpancy\vga4.rpt
vga4
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - -- INPUT G 0 0 0 0 clk50
55 - - - -- INPUT G 0 0 0 0 color
125 - - - -- INPUT G 0 0 0 0 mode_key
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\max2workpancy\vga4.rpt
vga4
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
12 - - A -- OUTPUT 0 1 0 0 b
26 - - C -- OUTPUT 0 1 0 0 g
28 - - C -- OUTPUT 0 1 0 0 hs
9 - - A -- OUTPUT 0 1 0 0 r
7 - - A -- OUTPUT 0 1 0 0 vs
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\max2workpancy\vga4.rpt
vga4
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 05 OR2 ! 0 2 0 4 |LPM_ADD_SUB:164|addcore:adder|:83
- 5 - C 03 AND2 0 3 0 4 |LPM_ADD_SUB:164|addcore:adder|:95
- 8 - C 03 AND2 0 2 0 1 |LPM_ADD_SUB:164|addcore:adder|:99
- 6 - C 03 AND2 0 4 0 2 |LPM_ADD_SUB:164|addcore:adder|:107
- 6 - A 23 AND2 0 2 0 5 |LPM_ADD_SUB:681|addcore:adder|:83
- 2 - A 22 AND2 0 3 0 3 |LPM_ADD_SUB:681|addcore:adder|:91
- 1 - A 13 AND2 0 3 0 3 |LPM_ADD_SUB:681|addcore:adder|:99
- 6 - A 13 AND2 0 3 0 2 |LPM_ADD_SUB:681|addcore:adder|:107
- 3 - C 13 DFFE 0 5 1 0 :4
- 4 - A 22 DFFE 0 5 1 0 :6
- 2 - C 16 DFFE 0 3 1 2 :8
- 1 - C 18 DFFE 0 3 1 2 :10
- 6 - C 18 DFFE 0 3 1 2 :12
- 5 - C 04 DFFE + 0 0 0 15 clk25 (:14)
- 3 - C 03 DFFE 0 4 0 17 cclk9 (:15)
- 4 - C 03 DFFE 0 3 0 16 cclk8 (:16)
- 2 - C 03 DFFE 0 4 0 13 cclk7 (:17)
- 1 - C 03 DFFE 0 4 0 18 cclk6 (:18)
- 7 - C 03 DFFE 0 3 0 20 cclk5 (:19)
- 6 - C 09 DFFE 0 4 0 12 cclk4 (:20)
- 8 - C 09 DFFE 0 3 0 11 cclk3 (:21)
- 6 - C 05 DFFE 0 3 0 7 cclk2 (:22)
- 7 - C 05 DFFE 0 3 0 3 cclk1 (:23)
- 5 - C 05 DFFE 0 2 0 3 cclk0 (:24)
- 4 - C 13 DFFE 0 5 0 11 hs2 (:25)
- 7 - A 13 DFFE 0 4 0 14 vclk9 (:26)
- 3 - A 13 DFFE 0 3 0 15 vclk8 (:27)
- 8 - A 13 DFFE 0 4 0 17 vclk7 (:28)
- 2 - A 13 DFFE 0 3 0 11 vclk6 (:29)
- 5 - A 13 DFFE 0 4 0 10 vclk5 (:30)
- 4 - A 13 DFFE 0 3 0 18 vclk4 (:31)
- 7 - A 22 DFFE 0 4 0 14 vclk3 (:32)
- 8 - A 22 DFFE 0 3 0 10 vclk2 (:33)
- 8 - A 14 DFFE 0 3 0 7 vclk1 (:34)
- 3 - A 14 DFFE 0 2 0 6 vclk0 (:35)
- 7 - C 15 DFFE + 0 2 0 5 flag2 (:36)
- 3 - C 15 DFFE + 0 2 0 5 flag1 (:37)
- 2 - C 15 DFFE + 0 2 0 5 flag0 (:38)
- 1 - C 17 DFFE + 0 1 0 6 flag21 (:42)
- 2 - C 24 DFFE + 0 0 0 7 flag20 (:43)
- 3 - C 01 OR2 0 3 0 10 :195
- 5 - C 01 OR2 0 3 0 1 :202
- 1 - C 13 AND2 ! 0 3 0 2 :411
- 8 - C 21 OR2 ! 0 2 0 4 :418
- 2 - C 13 OR2 s 0 4 0 2 ~443~1
- 2 - A 14 OR2 s 0 3 0 1 ~712~1
- 5 - A 14 OR2 ! 0 4 0 10 :712
- 6 - C 15 OR2 0 3 0 2 :1289
- 4 - C 15 OR2 0 3 0 2 :1313
- 1 - C 15 OR2 0 3 0 2 :1337
- 3 - C 24 AND2 0 2 0 3 :1456
- 3 - C 23 OR2 ! 0 4 0 1 :1643
- 8 - C 05 OR2 ! 0 4 0 1 :1658
- 2 - C 23 AND2 ! 0 4 0 1 :1751
- 1 - C 23 OR2 ! 0 3 0 1 :1768
- 4 - C 23 OR2 s ! 0 4 0 1 ~1856~1
- 8 - C 23 OR2 ! 0 3 0 3 :1856
- 1 - C 24 AND2 0 2 0 3 :1871
- 6 - A 16 OR2 ! 0 4 0 3 :2019
- 1 - A 15 AND2 s ! 0 2 0 4 ~2032~1
- 7 - A 16 OR2 ! 0 2 0 1 :2039
- 7 - A 24 AND2 s 0 2 0 5 ~2076~1
- 4 - A 21 OR2 0 4 0 3 :2076
- 8 - A 21 OR2 0 3 0 1 :2099
- 2 - A 24 OR2 ! 0 4 0 3 :2133
- 4 - A 24 OR2 ! 0 4 0 1 :2148
- 1 - A 24 OR2 0 3 0 1 :2156
- 8 - A 23 AND2 0 3 0 4 :2163
- 3 - A 22 OR2 0 4 0 3 :2193
- 1 - A 21 OR2 s 0 2 0 3 ~2195~1
- 6 - A 21 OR2 s 0 2 0 3 ~2195~2
- 1 - A 22 OR2 ! 0 2 0 2 :2215
- 5 - A 17 OR2 ! 0 4 0 3 :2247
- 8 - A 16 OR2 ! 0 4 0 1 :2260
- 3 - A 16 OR2 ! 0 2 0 3 :2272
- 3 - A 17 OR2 0 4 0 2 :2304
- 5 - A 21 OR2 0 4 0 1 :2314
- 8 - A 24 OR2 s 0 3 0 1 ~2364~1
- 5 - A 24 OR2 0 4 0 1 :2376
- 6 - A 22 AND2 ! 0 2 0 4 :2416
- 1 - A 14 OR2 s ! 0 3 0 1 ~2418~1
- 5 - A 22 OR2 ! 0 4 0 2 :2418
- 1 - A 23 OR2 ! 0 3 0 4 :2451
- 8 - A 17 OR2 0 4 0 1 :2538
- 4 - A 17 OR2 0 4 0 1 :2558
- 7 - A 17 OR2 0 4 0 1 :2577
- 2 - A 17 OR2 0 4 0 1 :2583
- 3 - A 24 OR2 s 0 4 0 2 ~2601~1
- 6 - A 17 OR2 0 4 0 1 :2609
- 1 - A 17 OR2 0 4 0 1 :2615
- 7 - C 13 OR2 ! 0 4 0 2 :2722
- 6 - C 20 OR2 0 4 0 3 :2779
- 1 - C 21 OR2 0 3 0 3 :2797
- 7 - C 22 OR2 ! 0 4 0 3 :2836
- 2 - C 01 OR2 s ! 0 3 0 3 ~2896~1
- 7 - C 19 OR2 0 4 0 3 :2896
- 8 - C 19 OR2 ! 0 3 0 3 :2950
- 5 - C 20 OR2 0 4 0 3 :3007
- 8 - C 22 OR2 0 4 0 2 :3064
- 4 - C 22 AND2 0 2 0 3 :3079
- 7 - C 20 OR2 ! 0 4 0 5 :3124
- 2 - C 21 OR2 0 2 0 3 :3144
- 4 - C 20 OR2 0 3 0 1 :3243
- 3 - C 19 OR2 s 0 4 0 1 ~3261~1
- 7 - C 17 OR2 0 4 0 1 :3265
- 8 - C 20 OR2 s 0 4 0 1 ~3280~1
- 1 - C 19 OR2 0 4 0 1 :3288
- 3 - C 20 OR2 0 4 0 1 :3304
- 6 - C 19 OR2 0 4 0 1 :3310
- 6 - A 20 AND2 ! 0 2 0 4 :3801
- 8 - A 20 AND2 0 4 0 1 :3833
- 1 - A 16 AND2 0 2 0 1 :3851
- 1 - A 20 OR2 s 0 4 0 1 ~3948~1
- 3 - A 23 OR2 ! 0 4 0 3 :3974
- 2 - A 23 OR2 0 3 0 2 :4043
- 3 - A 20 OR2 ! 0 4 0 2 :4084
- 5 - A 20 OR2 s 0 4 0 1 ~4351~1
- 7 - A 20 OR2 0 4 0 1 :4351
- 4 - A 20 OR2 0 4 0 4 :4363
- 1 - C 09 AND2 ! 0 4 0 1 :4439
- 7 - C 09 OR2 ! 0 4 0 1 :4496
- 5 - C 22 AND2 s ! 0 2 0 1 ~4541~1
- 2 - C 09 OR2 ! 0 4 0 1 :4559
- 4 - C 05 OR2 ! 0 2 0 6 :4571
- 1 - C 20 OR2 s 0 2 0 3 ~4598~1
- 2 - C 20 OR2 ! 0 2 0 3 :4598
- 3 - C 09 OR2 ! 0 4 0 1 :4643
- 5 - C 13 OR2 ! 0 4 0 1 :4661
- 3 - C 05 OR2 ! 0 4 0 3 :4679
- 6 - C 13 OR2 ! 0 4 0 1 :4758
- 4 - C 09 OR2 s 0 4 0 1 ~4800~1
- 8 - C 13 OR2 s 0 4 0 4 ~4800~2
- 5 - C 09 AND2 s ! 0 2 0 1 ~4907~1
- 1 - C 22 OR2 0 4 0 1 :4907
- 2 - C 22 OR2 s ! 0 3 0 2 ~4939~1
- 3 - C 22 OR2 0 4 0 3 :4939
- 4 - C 19 OR2 0 4 0 1 :5009
- 5 - C 19 OR2 s 0 4 0 1 ~5054~1
- 2 - C 19 OR2 0 4 0 3 :5054
- 4 - C 01 AND2 s 0 3 0 2 ~5129~1
- 1 - C 05 AND2 0 3 0 2 :5149
- 6 - C 01 OR2 s 0 4 0 1 ~5169~1
- 7 - C 01 OR2 s 0 3 0 1 ~5169~2
- 1 - C 01 OR2 s 0 4 0 4 ~5169~3
- 7 - A 21 OR2 0 3 0 1 :5263
- 3 - A 21 OR2 0 3 0 1 :5278
- 5 - A 23 OR2 0 3 0 2 :5320
- 4 - A 23 OR2 0 3 0 1 :5330
- 2 - A 21 OR2 s ! 0 4 0 2 ~5355~1
- 2 - A 16 OR2 0 3 0 1 :5428
- 7 - A 23 AND2 0 3 0 1 :5450
- 5 - A 16 OR2 s ! 0 4 0 1 ~5470~1
- 7 - A 14 AND2 0 2 0 1 :5494
- 4 - A 14 OR2 0 4 0 1 :5512
- 2 - A 20 AND2 ! 0 2 0 1 :5549
- 6 - A 24 OR2 0 3 0 2 :5551
- 6 - A 14 OR2 s ! 0 4 0 1 ~5586~1
- 4 - A 16 OR2 0 4 0 3 :5587
- 5 - C 15 OR2 0 4 0 2 :5627
- 5 - C 14 OR2 0 4 0 2 :5633
- 8 - C 15 OR2 0 4 0 2 :5639
- 7 - C 14 OR2 0 4 0 1 :6604
- 1 - C 14 OR2 0 4 0 1 :6616
- 6 - C 14 OR2 0 4 0 1 :6622
- 2 - C 14 OR2 0 4 0 3 :6624
- 3 - C 14 OR2 0 4 0 1 :6628
- 4 - C 14 OR2 0 4 0 1 :6634
- 8 - C 14 OR2 0 4 0 1 :6640
- 8 - C 18 OR2 0 4 0 1 :6674
- 8 - C 17 OR2 0 4 0 1 :6675
- 5 - C 18 OR2 0 4 0 1 :6679
- 2 - C 17 AND2 s 0 3 0 2 ~6689~1
- 5 - C 17 OR2 0 4 0 1 :6689
- 4 - C 18 AND2 0 4 0 1 :6692
- 6 - C 17 OR2 0 4 0 1 :6693
- 7 - C 18 OR2 0 4 0 1 :6694
- 3 - C 17 OR2 0 4 0 1 :6704
- 2 - C 18 OR2 0 4 0 1 :6707
- 4 - C 17 OR2 0 4 0 1 :6708
- 3 - C 18 OR2 0 4 0 1 :6709
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\max2workpancy\vga4.rpt
vga4
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 0/ 48( 0%) 37/ 48( 77%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 32/ 96( 33%) 13/ 48( 27%) 43/ 48( 89%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
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