random.s

ARM开发的源码

#*********************************************************************************************
# NAME:		random.s		                                                     			 *
# Author: 	Embest						                             						 *
# Desc:	    Random number generator.This uses a 33-bit feedback shift register to generate a *
#           pseudo-randomly ordered sequence of numbers which repeats in a cycle of length   *
#           2^33 - 1                                                                         *
#           NOTE: randomseed should not be set to 0, otherwise a zero will be generated      *
#           continuously (not particularly random!).This is a good application of direct ARM *
#           assembler, because the 33-bit shift register can be implemented using RRX (which *
#           uses reg + carry).An ANSI C version would be less efficient as the compiler would* 
#           not use RRX.								     								 *		  				                                 *
# History:	Y.Y.W 2005.02.22									     										 *
#			                                                                     			 *
#*********************************************************************************************

/*------------------------------------------------------------------------------------------*/
/*	 							 global symbol define			 				            */
/*------------------------------------------------------------------------------------------*/
	.global	randomnumber
	.global	__gccmain
	.global	seed
	
/*------------------------------------------------------------------------------------------*/
/*	 								code								 				    */
/*------------------------------------------------------------------------------------------*/
	.text
randomnumber:
# on exit:
# a1 = low 32-bits of pseudo-random number
# a2 = high bit (if you want to know it)
	ldr     ip, seedpointer
	ldmia   ip, {a1, a2}
	tst     a2, a2, lsr#1           /* to bit into carry	*/
	movs    a3, a1, rrx             /* 33-bit rotate right  */
	adc     a2, a2, a2              /* carry into LSB of a2 */
	eor     a3, a3, a1, lsl#12      /* (involved!)          */
	eor     a1, a3, a3, lsr#20      /* (similarly involved!)*/
	stmia   ip, {a1, a2}
	
	mov     pc, lr
	
seedpointer:
	.long    seed
	
__gccmain:
	mov	    pc, lr   
	
	.data
seed:
	.long    0x55555555
	.long    0x55555555

    .end