memap.h

瑞芯微RK2608固件源代码

#ifndef _MEMAP_H
#define	_MEMAP_H

#define       ZSP_STACK           0xbfff

#define       LCD_COMMAND         ((0x1f900     )/2)
#define       LCD_DATA            ((0x1f900+0x04)/2)
#define       LCD_DATA1           ( 0x10000        )


#define       FLASH0_DATA         ((0x1fa00     )/2)
#define       FLASH0_ADDR         ((0x1fa00+0x04)/2)
#define       FLASH0_CMD          ((0x1fa00+0x08)/2)
#define       FLASH1_DATA         ((0x1fb00     )/2)
#define       FLASH1_ADDR         ((0x1fb00+0x04)/2)
#define       FLASH1_CMD          ((0x1fb00+0x08)/2)


#define       EXT_REG_BASE         0x1f800
#define       ECC0                ((EXT_REG_BASE+0x00)/2)
#define       ECC1                ((EXT_REG_BASE+0x04)/2)
#define       ECC2                ((EXT_REG_BASE+0x08)/2)
#define       ECC3                ((EXT_REG_BASE+0x0c)/2)
#define       ECCCTL              ((EXT_REG_BASE+0x10)/2)
#define       FMCTL               ((EXT_REG_BASE+0x14)/2)
#define       CFWAIT              ((EXT_REG_BASE+0x18)/2)
#define       FMWAIT              ((EXT_REG_BASE+0x1c)/2)
#define       LCDWAIT             ((EXT_REG_BASE+0x20)/2)
#define       SYSCTL              ((EXT_REG_BASE+0x24)/2)

#define       SDRAM_BASE          (0x4000000/2)
#define       ZSPMEM_BASE         (0x20000/2  )
#define       USB_BASE            (0x1e000/2  )
#define       EXTMEM_BASE         (0x00000/2  )
#define       EXTMEM_BASE2        (0x80000/2  )
#define       I2C_BASE            (0x1e800/2  )
#define       WDT_BASE            (0x1e400/2  )
                                        
                                        
#define       DW_APB_I2C_BASE     0x1e800
#define       IC_CON              ((DW_APB_I2C_BASE + 0x00)/2)   //  R/W  [5:0]   0x04
#define       IC_TAR              ((DW_APB_I2C_BASE + 0x04)/2)   //  R/W  [11:0]  0x55
#define       IC_SAR              ((DW_APB_I2C_BASE + 0x08)/2)   //  R/W  [9:0]   0x55
#define       IC_HS_MADDR         ((DW_APB_I2C_BASE + 0x0c)/2)
#define       IC_DATA_CMD         ((DW_APB_I2C_BASE + 0x10)/2)   //  R/W  [8:0]   0x0
#define       IC_SS_HCNT          ((DW_APB_I2C_BASE + 0x14)/2)   //  R/W  [15:0]  0x60
#define       IC_SS_LCNT          ((DW_APB_I2C_BASE + 0x18)/2)   //  R/W  [15:0]  0x80
#define       IC_FS_HCNT          ((DW_APB_I2C_BASE + 0x1c)/2)   //  R/W  [15:0]  0x10
#define       IC_FS_LCNT          ((DW_APB_I2C_BASE + 0x20)/2)   //  R/W  [15:0]  0x22
#define       IC_HS_HCNT          ((DW_APB_I2C_BASE + 0x24)/2)
#define       IC_HS_LCNT          ((DW_APB_I2C_BASE + 0x28)/2)
#define       IC_INTR_STAT        ((DW_APB_I2C_BASE + 0x2c)/2)
#define       IC_INTR_MASK        ((DW_APB_I2C_BASE + 0x30)/2)
#define       IC_RAW_INTR_STAT    ((DW_APB_I2C_BASE + 0x34)/2)
#define       IC_RX_TL            ((DW_APB_I2C_BASE + 0x38)/2)
#define       IC_TX_TL            ((DW_APB_I2C_BASE + 0x3c)/2)
#define       IC_CLR_INTR         ((DW_APB_I2C_BASE + 0x40)/2)
#define       IC_CLR_RX_UNDER     ((DW_APB_I2C_BASE + 0x44)/2)
#define       IC_CLR_RX_OVER      ((DW_APB_I2C_BASE + 0x48)/2)
#define       IC_CLR_TX_OVER      ((DW_APB_I2C_BASE + 0x4c)/2)
#define       IC_CLR_RD_REQ       ((DW_APB_I2C_BASE + 0x50)/2)
#define       IC_CLR_TX_ABRT      ((DW_APB_I2C_BASE + 0x54)/2)
#define       IC_CLR_RX_DONE      ((DW_APB_I2C_BASE + 0x58)/2)
#define       IC_CLR_ACTIVITY     ((DW_APB_I2C_BASE + 0x5c)/2)
#define       IC_CLR_STOP_DET     ((DW_APB_I2C_BASE + 0x60)/2)
#define       IC_CLR_START_DET    ((DW_APB_I2C_BASE + 0x64)/2)
#define       IC_CLR_GEN_CALL     ((DW_APB_I2C_BASE + 0x68)/2)
#define       IC_ENABLE           ((DW_APB_I2C_BASE + 0x6c)/2)
#define       IC_STATUS           ((DW_APB_I2C_BASE + 0x70)/2)   //  R    [4:0]   0x6
#define       IC_TXFLR            ((DW_APB_I2C_BASE + 0x74)/2)
#define       IC_RXFLR            ((DW_APB_I2C_BASE + 0x78)/2)
#define       IC_SRESET           ((DW_APB_I2C_BASE + 0x7c)/2)
#define       IC_TX_ABRT_SOURCE   ((DW_APB_I2C_BASE + 0x80)/2)
#define       IC_VERSION_ID       ((DW_APB_I2C_BASE + 0xf8)/2)
#define       IC_DMA_CR           ((DW_APB_I2C_BASE + 0x88)/2)
#define       IC_DMA_TDLR         ((DW_APB_I2C_BASE + 0x8c)/2)
#define       IC_DMA_RDLR         ((DW_APB_I2C_BASE + 0x90)/2)
#define       I2CPING_1BIT_WR     ((IC_TAR)/2                )


#define       DMACBASE            0x1fc00                //  R/W     Width   Reset Value
#define       DMAR_SAR0           ((DMACBASE+0x000)/2)     //  R/W     32   0x0
#define       DMAR_DAR0           ((DMACBASE+0x008)/2)     //  R/W     32   0x0
#define       DMAR_CTL0           ((DMACBASE+0x018)/2)     //  R/W     64   0x00000002_00004825
#define       DMAR_CFG0           ((DMACBASE+0x040)/2)     //  R/W     64   0x00000004_00000c00
#define       DMAR_SGR0           ((DMACBASE+0x048)/2)     //  R/W     32   0x0
#define       DMAR_DSR0           ((DMACBASE+0x050)/2)     //  R/W     32   0x0
#define       DMAR_SAR1           ((DMACBASE+0x058)/2)     //  R/W     32   0x0
#define       DMAR_DAR1           ((DMACBASE+0x060)/2)     //  R/W     32   0x0
#define       DMAR_CTL1           ((DMACBASE+0x070)/2)     //  R/W     64   0x00000002_00004825
#define       DMAR_CFG1           ((DMACBASE+0x098)/2)     //  R/W     64   0x00000004_00000c20
#define       DMAR_SGR1           ((DMACBASE+0x0a0)/2)     //  R/W     32   0x0
#define       DMAR_DSR1           ((DMACBASE+0x0a8)/2)     //  R/W     32   0x0
#define       DMAR_SAR2           ((DMACBASE+0x0b0)/2)     //  R/W     32   0x0
#define       DMAR_DAR2           ((DMACBASE+0x0b8)/2)     //  R/W     32   0x0
#define       DMAR_CTL2           ((DMACBASE+0x0c8)/2)     //  R/W     64   0x00000002_00004825     
#define       DMAR_CFG2           ((DMACBASE+0x0f0)/2)     //  R/W     64   0x00000004_00000c40     
#define       DMAR_SGR2           ((DMACBASE+0x0f8)/2)     //  R/W     32   0x0
#define       DMAR_DSR2           ((DMACBASE+0x100)/2)     //  R/W     32   0x0
#define       DMAR_RawBlock       ((DMACBASE+0x2c8)/2)     //  R       3    0x0
#define       DMAR_RawSrcTran     ((DMACBASE+0x2d0)/2)     //  R       3    0x0
#define       DMAR_RawDstTran     ((DMACBASE+0x2d8)/2)     //  R       3    0x0
#define       DMAR_RawErr         ((DMACBASE+0x2e0)/2)     //  R       3    0x0
#define       DMAR_RawTfr         ((DMACBASE+0x2c0)/2)     //  R       3    0x0
#define       DMAR_StatusTfr      ((DMACBASE+0x2e8)/2)     //  R       3    0x0
#define       DMAR_StatusBlock    ((DMACBASE+0x2f0)/2)     //  R       3    0x0
#define       DMAR_StatusBlock    ((DMACBASE+0x2f0)/2)     //  R       3    0x0
#define       DMAR_StatusSrcTran  ((DMACBASE+0x2f8)/2)     //  R       3    0x0
#define       DMAR_StatusDstTran  ((DMACBASE+0x300)/2)     //  R       3    0x0
#define       DMAR_StatusErr      ((DMACBASE+0x308)/2)     //  R       3    0x0
#define       DMAR_MaskTfr        ((DMACBASE+0x310)/2)     //  R/W     3-3  0x0
#define       DMAR_MaskBlock      ((DMACBASE+0x318)/2)     //  R/W     3-3  0x0
#define       DMAR_MaskSrcTran    ((DMACBASE+0x320)/2)     //  R/W     3-3  0x0
#define       DMAR_MaskDstTran    ((DMACBASE+0x328)/2)     //  R/W     3-3  0x0
#define       DMAR_MaskErr        ((DMACBASE+0x330)/2)     //  R/W     3-3  0x0
#define       DMAR_ClearTfr       ((DMACBASE+0x338)/2)     //  W       3    0x0
#define       DMAR_ClearBlock     ((DMACBASE+0x340)/2)     //  W       3    0x0
#define       DMAR_ClearSrcTran   ((DMACBASE+0x348)/2)     //  W       3    0x0
#define       DMAR_ClearDstTran   ((DMACBASE+0x350)/2)     //  W       3    0x0
#define       DMAR_ClearErr       ((DMACBASE+0x358)/2)     //  W       3    0x0
#define       DMAR_StatusInt      ((DMACBASE+0x360)/2)     //  W       5    0x0
#define       DMAR_ReqSrcReg      ((DMACBASE+0x368)/2)     //  R/W     3-3  0x0
#define       DMAR_ReqDstReg      ((DMACBASE+0x370)/2)     //  R/W     3-3  0x0