prev_cmp_bahe.tan.qmsg

带获胜音乐的拔河游戏机

{ "Info" "ITDB_TSU_RESULT" "cmp:com\|tmp_sta reset clk_in 2.000 ns register " "Info: tsu for register \"cmp:com\|tmp_sta\" (data pin = \"reset\", clock pin = \"clk_in\") is 2.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns reset 1 PIN PIN_2 24 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_2; Fanout = 24; PIN Node = 'reset'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "bahe.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/bahe.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns cmp:com\|tmp_sta 2 REG LC106 25 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC106; Fanout = 25; REG Node = 'cmp:com\|tmp_sta'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.000 ns" { reset cmp:com|tmp_sta } "NODE_NAME" } } { "cmp.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/cmp.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 90.00 % ) " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.00 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { reset cmp:com|tmp_sta } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { reset reset~out cmp:com|tmp_sta } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "cmp.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/cmp.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 12.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_in\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk_in 1 CLK PIN_83 55 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 55; CLK Node = 'clk_in'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "bahe.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/bahe.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns division:div\|clk2 2 REG LC50 14 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC50; Fanout = 14; REG Node = 'division:div\|clk2'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { clk_in division:div|clk2 } "NODE_NAME" } } { "division.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/division.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns cmp:com\|tmp_sta 3 REG LC106 25 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC106; Fanout = 25; REG Node = 'cmp:com\|tmp_sta'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { division:div|clk2 cmp:com|tmp_sta } "NODE_NAME" } } { "cmp.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/cmp.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk_in division:div|clk2 cmp:com|tmp_sta } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk_in clk_in~out division:div|clk2 cmp:com|tmp_sta } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { reset cmp:com|tmp_sta } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { reset reset~out cmp:com|tmp_sta } { 0.000ns 0.000ns 1.000ns } { 0.000ns 3.000ns 6.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.000 ns" { clk_in division:div|clk2 cmp:com|tmp_sta } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.000 ns" { clk_in clk_in~out division:div|clk2 cmp:com|tmp_sta } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in led\[7\] cmp:com\|tmp\[2\] 35.000 ns register " "Info: tco from clock \"clk_in\" to destination pin \"led\[7\]\" through register \"cmp:com\|tmp\[2\]\" is 35.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 21.000 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to source register is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk_in 1 CLK PIN_83 55 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 55; CLK Node = 'clk_in'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "bahe.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/bahe.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns division:div\|clk2 2 REG LC50 14 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC50; Fanout = 14; REG Node = 'division:div\|clk2'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { clk_in division:div|clk2 } "NODE_NAME" } } { "division.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/division.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns division:div\|clk3 3 REG LC1 15 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC1; Fanout = 15; REG Node = 'division:div\|clk3'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { division:div|clk2 division:div|clk3 } "NODE_NAME" } } { "division.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/division.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns cmp:com\|tmp\[2\] 4 REG LC18 17 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC18; Fanout = 17; REG Node = 'cmp:com\|tmp\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { division:div|clk3 cmp:com|tmp[2] } "NODE_NAME" } } { "cmp.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/cmp.vhd" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "17.000 ns ( 80.95 % ) " "Info: Total cell delay = 17.000 ns ( 80.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 19.05 % ) " "Info: Total interconnect delay = 4.000 ns ( 19.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "21.000 ns" { clk_in division:div|clk2 division:div|clk3 cmp:com|tmp[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "21.000 ns" { clk_in clk_in~out division:div|clk2 division:div|clk3 cmp:com|tmp[2] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "cmp.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/cmp.vhd" 63 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cmp:com\|tmp\[2\] 1 REG LC18 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC18; Fanout = 17; REG Node = 'cmp:com\|tmp\[2\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { cmp:com|tmp[2] } "NODE_NAME" } } { "cmp.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/cmp.vhd" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns decode:dec\|Mux6~95 2 COMB LC61 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC61; Fanout = 1; COMB Node = 'decode:dec\|Mux6~95'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { cmp:com|tmp[2] decode:dec|Mux6~95 } "NODE_NAME" } } { "decode.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/decode.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns led\[7\] 3 PIN PIN_34 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'led\[7\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { decode:dec|Mux6~95 led[7] } "NODE_NAME" } } { "bahe.vhd" "" { Text "D:/VHDL+拔河游戏机/bahe/bahe.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns ( 84.62 % ) " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { cmp:com|tmp[2] decode:dec|Mux6~95 led[7] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { cmp:com|tmp[2] decode:dec|Mux6~95 led[7] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "21.000 ns" { clk_in division:div|clk2 division:div|clk3 cmp:com|tmp[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "21.000 ns" { clk_in clk_in~out division:div|clk2 division:div|clk3 cmp:com|tmp[2] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 6.000ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.000 ns" { cmp:com|tmp[2] decode:dec|Mux6~95 led[7] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.000 ns" { cmp:com|tmp[2] decode:dec|Mux6~95 led[7] } { 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 4.000ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_